trabajo vhdl
TRANSCRIPT
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Vhdl semaforo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity semaforo is
Port ( clk : in STD_LOGIC;
luces : out STD_LOGIC_VECTOR (11 downto 0));
end semaforo;
architecture Behavioral of semaforo is
type estados is (s0,s1,s2,s3,s4,s5,s6,s7);
signal q,qmas: estados;
signal cuenta: STD_LOGIC_VECTOR(6 downto 0);
constant verderojo: STD_LOGIC_VECTOR(6 downto 0):= "1111000";
constant amarillo: STD_LOGIC_VECTOR(6 downto 0):= "0001111";
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begin
process(clk,q,cuenta)
begin
if (clk'event and clk= '1') then
q
if cuenta < verderojo then
qmas
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else
qmas
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if cuenta < amarillo then
qmas
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Funcion_de_salida: process(q)
begin
case q is
when s0 =>
luces
luces
luces
luces
luces
luces
luces
luces
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vhdl alu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu is
Port ( A : in STD_LOGIC_VECTOR (4 downto 0);
B : in STD_LOGIC_VECTOR (4 downto 0);
G: in STD_LOGIC_VECTOR(2 downto 0);
z : out STD_LOGIC_VECTOR (4 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(G,A,B)
begin
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case G is
when "000" => z z z z z z z z z
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-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity maquinas is
Port ( clk : in STD_LOGIC;
y : in STD_LOGIC;
m : out STD_LOGIC_VECTOR (3 downto 0));
end maquinas;
architecture Behavioral of maquinas is
type estados is (s0,s1,s2,s3,s4,s5,s6);
signal q,qmas : estados;
signal cuenta: STD_LOGIC_VECTOR(5 downto 0);
constant sesenta: STD_LOGIC_VECTOR(5 downto 0):="111100";
constant treinta: STD_LOGIC_VECTOR(5 downto 0):="011110";
begin
process (clk,y,cuenta,q)
begin
if (clk'event and clk = '1') then
q
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end if;
case q is
when S0 =>
if cuenta < sesenta then
qmas
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end if;
when S2 =>
if cuenta < sesenta then
qmas
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when S4 =>
if cuenta < treinta then
qmas
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when S6 =>
if cuenta < treinta then
qmas
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m
m
m
m
m
m
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--library UNISIM;
--use UNISIM.VComponents.all;
entity bcd is
Port ( clk : in STD_LOGIC;
S : in STD_LOGIC;
contador : out STD_LOGIC_VECTOR (3 downto 0));
end bcd;
architecture Behavioral of bcd is
type estados is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal q,qmas :estados;
begin
process(clk)
begin
if (clk'event and clk = '1') then
q
if S = '1' then
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qmas
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else
qmas
if S = '1' then
qmas
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qmas
if S = '1' then
qmas
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contador
contador
contador
contador
contador
contador
contador