anexos - bibing.us.esbibing.us.es/proyectos/abreproy/11375/fichero/memoria%2fanexos.pdf · anexos...

ANEXOS 104

José Manuel Marín de la Rosa

ANEXOS

ANEXOS 105


CÓDIGOS VHDL PARA FILTRO FIR.

1.- Top del filtro FIR. (acrhivo fir2.vhd)

-------------------------------------- ------------------------------------------------------------- Filtro Fir: -- Señal digital de entrada de 18 bits -- Coeficientes de 9 Bits -- Multiplicadores de 18X9 (tantos como coef. se tengan, o sea, tantos como retrasos halla) -- Acumulador (sumador) de dichas multiplicaciones -- Filtro paso de baja tipo Butterworth, con frecuencia de corte de 5 Khz -- Caso 1: Filtro fir sin redundar -------------------------------------------------------------------------------------------------- -- Bloque para describir los coeficientes del filtro FIR library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package fir_coef is subtype coef_word is signed(8 downto 0);--coeficientes de 9 bits subtype coef_range is integer range 0 to 10; --numero de coeficientes que hay, o sea, retrasos type coef_table is array (0 to 10) of coef_word; constant coef_rom: coef_table:= ( ("111111110"), ("111111110"), ("000000110"), ("000110010"), ("001110110"), ("010011010"), ("001110110"), ("000110010"), ("000000110"), ("111111110"), ("111111110")); end package fir_coef;

ANEXOS 106


-- Filtro Fir library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.fir_coef.all; entity fir is port (clk,reset,load: in std_logic; data_in: in std_logic_vector(17 downto 0); -- señal digital de entrada de 20 bits data_out: out std_logic_vector(17 downto 0); ultima_etapa: out std_logic_vector(17 downto 0)); end fir; architecture a_fir of fir is type fifo_array is array (0 to 10) of signed (17 downto 0); signal fifo,p_fifo: fifo_array; signal data_outi: std_logic_vector(17 downto 0); component regTmr is Generic(N:integer:=18); Port ( clk : in std_logic; reset : in std_logic; d : in signed (N-1 downto 0); q : out signed (N-1 downto 0)); end component; component regSimple is Generic(N:integer:=18); Port ( clk : in std_logic; reset : in std_logic; d : in signed (N-1 downto 0); q : out signed (N-1 downto 0)); end component; begin sinc:process (reset,clk) begin if reset = '1' then data_out <= (others => '0');

ANEXOS 107


elsif clk'event and clk = '1' then data_out <= data_outi; end if; end process sinc; r0: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(0), q => fifo(0)); r1: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(1), q => fifo(1)); r2: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(2), q => fifo(2)); r3: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(3), q => fifo(3)); r4: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(4), q => fifo(4)); r5: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(5), q => fifo(5)); r6: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(6), q => fifo(6)); r7: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(7), q => fifo(7)); r8: regSimple Generic map (N=>18)

ANEXOS 108


port map (clk => clk, reset => reset, d => p_fifo(8), q => fifo(8)); r9: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(9), q => fifo(9)); r10: regSimple Generic map (N=>18) port map (clk => clk, reset => reset, d => p_fifo(10), q => fifo(10)); regs: process(load,fifo,data_in) begin if load = '1' then for i in 1 to 10 loop p_fifo(i) <= fifo(i-1); end loop; p_fifo (0) <= signed (data_in); else for i in 0 to 10 loop p_fifo(i) <= fifo(i); end loop; end if; end process regs; firstruct: process (fifo) variable prod: signed (26 downto 0); variable idata_tmp: signed (19 downto 0); variable data_tmp: signed (17 downto 0); begin data_tmp := (others => '0'); for i in 0 to 10 loop prod := fifo(i) * coef_rom(i); if (prod(26)='1') then prod:=prod+255; --redondeo end if; idata_tmp := (data_tmp(17)&data_tmp(17)&data_tmp) + (prod(26)&prod(26)&prod(26 downto 9)); if idata_tmp(19 downto 18) = "01" then --significa que desborda por arriba data_tmp:=(17=>'0',others=>'1'); elsif idata_tmp(19 downto 18) = "10" then --significa que desborda por abajo data_tmp:=(17=>'1',others=>'0'); else data_tmp:=idata_tmp(17 downto 0);

ANEXOS 109


end if; end loop; data_outi <= std_logic_vector (data_tmp); end process firstruct; end a_fir; 2.- Componente registro simple. (Archivo regsimple.vhd) library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity regSimple is Generic(N:integer:=18); Port ( clk : in std_logic; reset : in std_logic; d : in signed(N-1 downto 0); q : out signed(N-1 downto 0)); end regSimple; architecture Behavioral of regSimple is begin sinc: process(reset,clk) begin if (reset='1') then q <= (others => '0'); elsif (clk'event) and (clk='1') then q <= d; end if; end process sinc; end Behavioral;

ANEXOS 110


3.- Componente registro con triple redundancia modular. (Archivo regTmr.vhd) library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity regTmr is Generic(N:integer:=18); Port ( clk : in std_logic; reset : in std_logic; d : in signed (N-1 downto 0); q : out signed (N-1 downto 0)); end regTmr; architecture Behavioral of regTmr is signal q_a,q_b,q_c:signed (N-1 downto 0); begin sinc: process(reset,clk) begin if (reset='1') then q_a <= (others => '0'); q_b <= (others => '0'); q_c <= (others => '0'); elsif (clk'event) and (clk='1') then q_a <= d; q_b <= d; q_c <= d; end if; end process sinc; q <= (q_a AND q_b) OR (q_a AND q_c) OR (q_b AND q_c); end Behavioral;

ANEXOS 111


4.- Códigos Test Bench. (Archivo TB_fir.vhd) -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:52:47 01/17/2007 -- Design Name: fir -- Module Name: C:/Proyectos/FIR_secure/FIR/TB_fir.vhd -- Project Name: FIR -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: fir -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; --USE ieee.numeric_std.ALL; USE std.textio.all; USE ieee.std_logic_textio.all; ENTITY TB_fir_vhd IS END TB_fir_vhd;

ANEXOS 112


ARCHITECTURE behavior OF TB_fir_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fir PORT( clk : IN std_logic; reset : IN std_logic; load : IN std_logic; data_in : IN std_logic_vector(17 downto 0); data_out : OUT std_logic_vector(17 downto 0); ultima_etapa : OUT std_logic_vector(17 downto 0) ); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL reset : std_logic := '1'; SIGNAL load : std_logic := '0'; SIGNAL data_in : std_logic_vector(17 downto 0) := (others=>'0'); --Outputs SIGNAL data_out : std_logic_vector(17 downto 0); SIGNAL ultima_etapa : std_logic_vector(17 downto 0); --FIcheros BEGIN -- Instantiate the Unit Under Test (UUT) uut: fir PORT MAP( clk => clk, reset => reset, load => load, data_in => data_in, data_out => data_out, ultima_etapa => ultima_etapa ); clk <= not clk after 50 ns; tb : PROCESS FILE infile: TEXT is IN "entradafir.txt"; FILE outfile: TEXT is OUT "ficherodesalida.txt"; VARIABLE lineaent,lineasal: LINE; VARIABLE aux:std_logic_vector(17 downto 0); VARIABLE auxi:integer; BEGIN WAIT FOR 100 ns; reset <='0'; WHile not(ENDFILE(infile))LOOP

ANEXOS 113


READLINE(infile,lineaent);-- LEE UNA LINEA DEL FICHERO DE ENTRADA READ(lineaent,auxi); aux:= conv_std_logic_vector(auxi,18); data_in<=aux; load<='1'; wait for 100 ns; WRITE(lineasal,data_out); WRITE(lineasal,' '); WRITE(lineasal,ultima_etapa); writeline(outfile,lineasal); load<='0'; wait for 200 ns; END LOOP; wait; END PROCESS; END behavior; 5.- Códigos Test Bench. (Archivo TB_fir.vhd) -- ADDED BY THE FTUNSHADES PROJECT ------------- -- THIS FILE HAS BEEN MODIFIED TO GENERATE THE TEST VECTORS; --GenerateTVG V2.0 -- FT UNSHADES TEAM: J. Tombs, M. Aguirre, V. Baena, F. Munoz; ---------------------------- -- ADDED BY THE FTUNSHADES PROJECT ------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE STD.TEXTIO.ALL; ---------------------------- -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:52:47 01/17/2007

ANEXOS 114


-- Design Name: fir -- Module Name: C:/Proyectos/FIR_secure/FIR/TB_fir.vhd -- Project Name: FIR -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: fir -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; --USE ieee.numeric_std.ALL; USE std.textio.all; USE ieee.std_logic_textio.all; ENTITY TB_fir_vhd IS END TB_fir_vhd; ARCHITECTURE behavior OF TB_fir_vhd IS -- ADDED BY THE FTUNSHADES PROJECT ------------- SIGNAL ftunshades_cont_vectors: natural :=0; SIGNAL ftunshades_endsim: std_logic :='L'; SIGNAL ftunshades_normalend:std_logic :='0'; SIGNAL ftunshades_remaining_mem: natural := 100; ---------------------------------------------------

ANEXOS 115


-- ADDED BY THE FTUNSHADES PROJECT ------------- SIGNAL ftunshades_cont_mem: natural := 0; SIGNAL ftunshades_cont_datas: natural := 0; SIGNAL ftunshades_data1: signed(19 downto 0); ---------------------------------------- -- Component Declaration for the Unit Under Test (UUT) COMPONENT fir PORT( clk : IN std_logic; reset : IN std_logic; load : IN std_logic; data_in : IN std_logic_vector(17 downto 0); data_out : OUT std_logic_vector(17 downto 0); ultima_etapa : OUT std_logic_vector(17 downto 0) ); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL reset : std_logic := '1'; SIGNAL load : std_logic := '0'; SIGNAL data_in : std_logic_vector(17 downto 0) := (others=>'0'); --Outputs SIGNAL data_out : std_logic_vector(17 downto 0); SIGNAL ultima_etapa : std_logic_vector(17 downto 0); --FIcheros BEGIN -- ADDED BY THE FTUNSHADES PROJECT ------------- assert (ftunshades_cont_mem<6291452) report "Memories full" severity warning; assert (ftunshades_cont_vectors<2147483647) report "Too many vectors" severity warning; assert (ftunshades_normalend = '0') report "Succesful test file generation" severity failure; ----------------------------------------

ANEXOS 116


-- ADDED BY THE FTUNSHADES PROJECT ------------- ftunshades_endsim <= '1' when (ftunshades_cont_mem>=6291452 or ftunshades_cont_vectors>=2147483647); ftunshades_remaining_mem <= (100*(6291456-ftunshades_cont_mem))/6291456; ---------------------------------------------- -- ADDED BY THE FTUNSHADES PROJECT ------------- process(clk) file vector_file: text open write_mode is "ftunshades_memory.dat"; variable dato1: signed(19 downto 0); variable DataLine: line; variable dato_integer: integer; begin if (reset='1' or reset='H') then dato1(0):='1'; else dato1(0):='0'; end if; if (load='1' or load='H') then dato1(1):='1'; else dato1(1):='0'; end if; if (data_in(17)='1' or data_in(17)='H') then dato1(2):='1'; else dato1(2):='0'; end if; if (data_in(16)='1' or data_in(16)='H') then dato1(3):='1'; else dato1(3):='0'; end if; if (data_in(15)='1' or data_in(15)='H') then dato1(4):='1'; else dato1(4):='0'; end if; if (data_in(14)='1' or data_in(14)='H') then

ANEXOS 117


dato1(5):='1'; else dato1(5):='0'; end if; if (data_in(13)='1' or data_in(13)='H') then dato1(6):='1'; else dato1(6):='0'; end if; if (data_in(12)='1' or data_in(12)='H') then dato1(7):='1'; else dato1(7):='0'; end if; if (data_in(11)='1' or data_in(11)='H') then dato1(8):='1'; else dato1(8):='0'; end if; if (data_in(10)='1' or data_in(10)='H') then dato1(9):='1'; else dato1(9):='0'; end if; if (data_in(9)='1' or data_in(9)='H') then dato1(10):='1'; else dato1(10):='0'; end if; if (data_in(8)='1' or data_in(8)='H') then dato1(11):='1'; else dato1(11):='0'; end if; if (data_in(7)='1' or data_in(7)='H') then dato1(12):='1'; else dato1(12):='0'; end if; if (data_in(6)='1' or data_in(6)='H') then dato1(13):='1'; else dato1(13):='0'; end if; if (data_in(5)='1' or data_in(5)='H') then dato1(14):='1'; else dato1(14):='0'; end if; if (data_in(4)='1' or data_in(4)='H') then

ANEXOS 118


dato1(15):='1'; else dato1(15):='0'; end if; if (data_in(3)='1' or data_in(3)='H') then dato1(16):='1'; else dato1(16):='0'; end if; if (data_in(2)='1' or data_in(2)='H') then dato1(17):='1'; else dato1(17):='0'; end if; if (data_in(1)='1' or data_in(1)='H') then dato1(18):='1'; else dato1(18):='0'; end if; if (data_in(0)='1' or data_in(0)='H') then dato1(19):='1'; else dato1(19):='0'; end if; if(clk='1' and clk'event) then ftunshades_data1<=dato1; if(ftunshades_cont_mem<6291456) then if(ftunshades_cont_datas=0) then ftunshades_cont_datas <= ftunshades_cont_datas+1; dato_integer:=20; write(DataLine,dato_integer); writeline(vector_file,DataLine); ftunshades_cont_vectors<=ftunshades_cont_vectors+1; elsif(ftunshades_data1=dato1 and ftunshades_cont_datas<65535 and ftunshades_endsim='L') then ftunshades_cont_datas<=ftunshades_cont_datas+1; ftunshades_cont_vectors<=ftunshades_cont_vectors+1; elsif((ftunshades_cont_datas=65535) or ((ftunshades_data1/=dato1) and ftunshades_cont_datas>1) or ftunshades_endsim='1') then dato_integer := 1; write(DataLine,dato_integer); write(DataLine,STRING'(" ")); dato_integer := ftunshades_cont_datas; write(DataLine,dato_integer); writeline(vector_file,DataLine); dato_integer := 0; write(DataLine,dato_integer);

ANEXOS 119


write(DataLine,STRING'(" ")); dato_integer := conv_integer(ftunshades_data1); write(DataLine,dato_integer); write(DataLine,STRING'(" ")); writeline(vector_file,DataLine); ftunshades_cont_mem<=ftunshades_cont_mem+2; ftunshades_cont_datas<=1; if (ftunshades_endsim='1') then dato_integer:=1; write(DataLine,dato_integer); write(DataLine,STRING'(" ")); dato_integer:=0; write(DataLine,dato_integer); writeline(vector_file,DataLine); dato_integer:=1; write(DataLine,dato_integer); write(DataLine,STRING'(" ")); dato_integer:=0; write(DataLine,dato_integer); writeline(vector_file,DataLine); dato_integer := conv_integer(ftunshades_cont_vectors); write(DataLine,dato_integer); writeline(vector_file,DataLine); ftunshades_normalend<='1'; end if; ftunshades_cont_vectors<=ftunshades_cont_vectors+1; else dato_integer := 0; write(DataLine,dato_integer); write(DataLine,STRING'(" ")); dato_integer := conv_integer(ftunshades_data1); write(DataLine,dato_integer); write(DataLine,STRING'(" ")); writeline(vector_file,DataLine); ftunshades_cont_mem<=ftunshades_cont_mem+1; ftunshades_cont_datas<=1; if (ftunshades_endsim='1') then dato_integer:=1; write(DataLine,dato_integer); write(DataLine,STRING'(" ")); dato_integer:=0; write(DataLine,dato_integer); writeline(vector_file,DataLine); dato_integer:=1; write(DataLine,dato_integer); write(DataLine,STRING'(" ")); dato_integer:=0; write(DataLine,dato_integer);

ANEXOS 120


writeline(vector_file,DataLine); dato_integer := conv_integer(ftunshades_cont_vectors); write(DataLine,dato_integer); writeline(vector_file,DataLine); ftunshades_normalend<='1'; end if; ftunshades_cont_vectors<=ftunshades_cont_vectors+1; end if; end if; end if; end process; ---------------------------- -- Instantiate the Unit Under Test (UUT) uut: fir PORT MAP( clk => clk, reset => reset, load => load, data_in => data_in, data_out => data_out, ultima_etapa => ultima_etapa ); clk <= not clk after 50 ns; tb : PROCESS FILE infile: TEXT is IN "entradafir.txt"; FILE outfile: TEXT is OUT "ficherodesalida.txt"; VARIABLE lineaent,lineasal: LINE; VARIABLE aux:std_logic_vector(17 downto 0); VARIABLE auxi:integer; BEGIN WAIT FOR 100 ns; reset <='0'; WHile not(ENDFILE(infile))LOOP READLINE(infile,lineaent);-- LEE UNA LINEA DEL FICHERO DE ENTRADA READ(lineaent,auxi); aux:= conv_std_logic_vector(auxi,18); data_in<=aux; load<='1'; wait for 100 ns; auxi:=conv_integer(data_out); WRITE(lineasal,auxi); WRITE(lineasal,' '); WRITE(lineasal,ultima_etapa);

ANEXOS 121


writeline(outfile,lineasal); load<='0'; wait for 200 ns; END LOOP; ftunshades_endsim<='1'; wait; END PROCESS; END behavior; FICHEROS DE PRUEBAS FILTRO FIR Son todos ficheros muy parecidos al fir2, tan sólo cambiando los registros simples por registrosTmr (con triple redundancia modular) en los sitios en los que se quieran insertar la triple redundancia. Por este motivo, y al ser muchos ficheros parecidos no veo conveniente introducirlos en este anexo pero si adjuntarlos en el cd de datos que uno a esta documentación.

ANEXOS 122


CÓDIGOS VHDL PARA FILTRO IIR.

7.- Top del filtro IIR. (acrhivo iir.vhd)

-----------------------------------------------------------

-----------------------------------------------------------

-- Filtro IIR:

-- Señal digital de entrada de 18 bits

-- Coeficientes de 9 Bits

-- Filtro paso de baja tipo Butterworth, con frecuencia

de corte de 5 Khz

-----------------------------------------------------------

-----------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

-- Filtro iir

library ieee;



use work.fir_coef.all;

entity iir is

port (clk,reset,load: in std_logic;

ANEXOS 123


data_in: in std_logic_vector(17 downto 0);

-- señal digital de entrada de 18 bits

data_out: out std_logic_vector(17 downto 0);

ultima_etapa: out std_logic_vector(17 downto 0));

end iir;

architecture a_iir of iir is

signal data_outi: std_logic_vector(17 downto 0);

signal data_outb, data_outa: signed (17 downto 0);

signal data_outbv, data_outav: std_logic_vector(17

downto 0);

component fir

Generic (es_a: integer:=0);






end component;

begin

fir_a: fir

generic map (es_a=>1)

port map (clk=>clk, reset=>reset, load=>load,

data_in=>data_outi, data_out=>data_outav);

data_outa <= signed (data_outav);

fir_b: fir

generic map (es_a=>0)

ANEXOS 124


port map (clk=>clk, reset=>reset, load=>load,

data_in=>data_in, data_out=>data_outbv);

data_outb <= signed (data_outbv);

firstruct: process (data_outa,data_outb)

variable idata_tmp: signed (19 downto 0);

variable data_tmp: signed (17 downto 0);

begin

idata_tmp :=

(data_outb(17)&data_outb(17)&data_outb(17 downto 0)) -

(data_outa&"00") ;

if idata_tmp(19 downto 18) = "01" then --

significa que desborda por arriba

data_tmp:=(17=>'0',others=>'1');

elsif idata_tmp(19 downto 18) = "10" then -

-significa que desborda por abajo


else

data_tmp:=idata_tmp(17 downto 0);

end if;

data_outi <= std_logic_vector (data_tmp);

end process firstruct;

data_out <= data_outi;

ultima_etapa <= (others =>'0');

end a_iir;

ANEXOS 125


8.- Componente Fir del filtro IIR. (acrhivo fir2i.vhd)

-----------------------------------------------------------

-----------------------------------------------------------

-- Filtro Fir:

-- Señal digital de entrada de 18 bits

-- Coeficientes de 9 Bits

-- Multiplicadores de 18X9 (tantos como coef. se tengan,

o sea, tantos como retrasos halla)

-- Acumulador (sumador) de dichas multiplicaciones

-- Filtro paso de baja tipo Butterworth, con frecuencia

de corte de 5 Khz

-----------------------------------------------------------

-----------------------------------------------------------

-- Bloque para describir los coeficientes del filtro FIR

library ieee;


--use ieee.std_logic_arith.all;

--use ieee.std_logic_signed.all;


package fir_coef is

subtype coef_word is signed(8 downto 0);

--coeficientes de 4 bits

subtype coef_range is integer range 0 to 4; --

numero de coeficientes que hay, o sea, retrasos

type coef_table is array (0 to 4) of coef_word;

constant coef_rom_a: coef_table:= (

ANEXOS 126


("101000011"),

("011101100"),

("101110010"),

("000100011"),

("000000000"));

constant coef_rom_b: coef_table:= (

("000010010"),

("111011111"),

("000101111"),

("111011111"),

("000010010"));

end package fir_coef;

-- Filtro fir

library ieee;



use work.fir_coef.all;

entity fir is

Generic (es_a: integer:=0);





ANEXOS 127



end fir;

architecture a_fir of fir is

type fifo_array is array (0 to 4) of signed (17 downto

0);

signal fifo,p_fifo: fifo_array;

signal data_outi: std_logic_vector(17 downto 0);

component regTmr is

Generic(N:integer:=18);

Port ( clk : in std_logic;

reset : in std_logic;

d : in signed (N-1 downto 0);

q : out signed (N-1 downto 0));

end component;

component regSimple is

Generic(N:integer:=18);

Port ( clk : in std_logic;

reset : in std_logic;

d : in signed (N-1 downto 0);

q : out signed (N-1 downto 0));

end component;

begin

sinc:process (reset,clk)

begin

if reset = '1' then

data_out <= (others => '0');

ANEXOS 128


-- for i in 0 to 10 loop

-- fifo (i) <= (others => '0');

-- end loop;

elsif clk'event and clk = '1' then

-- if load ='1' then

data_out <= data_outi;

-- end if;

-- for i in 0 to 10 loop

-- fifo(i) <= p_fifo(i);

-- end loop;

end if;

end process sinc;

r0: regsimple

Generic map (N=>18)

port map (clk => clk, reset => reset, d => p_fifo(0), q

=> fifo(0));

r1: regsimple

Generic map (N=>17)

port map (clk => clk, reset => reset, d => p_fifo(1)(17

downto 1), q => fifo(1)(17 downto 1));

r1s: regsimple

Generic map (N=>1)



ANEXOS 129


r2: regsimple

Generic map (N=>16)



r2s: regSimple

Generic map (N=>2)



r3: regsimple

Generic map (N=>15)



r3s: regSimple

Generic map (N=>3)



r4: regsimple

Generic map (N=>18)

port map (clk => clk, reset => reset, d => p_fifo(4), q

=> fifo(4));

g1: if (es_a=1)

generate

regs: process(load,fifo,data_in)

begin

if load = '1' then

ANEXOS 130


for i in 1 to 4 loop

p_fifo(i) <= fifo(i-1);

end loop;

p_fifo (0) <= signed (data_in);

else


p_fifo(i) <= fifo(i);

end loop;

end if;

end process regs;

firstruct: process (fifo)

variable prod: signed (26 downto 0);



begin

idata_tmp := (others => '0');


prod := fifo(i) * coef_rom_a(i);

if (prod(26)='1') then

prod:=prod+255; --redondeo

end if;

idata_tmp := idata_tmp +

(prod(26)&prod(26)&prod(26)&prod(26 downto 8));

end loop;

if idata_tmp(21) = '0' and idata_tmp(20

downto 17) /= "0000" then --significa que desborda por

arriba


ANEXOS 131


elsif idata_tmp(21) = '1' and idata_tmp(20

downto 17) /= "1111" then --significa que desborda por

abajo


else


end if;

-- end loop;



end generate;

g0: if (es_a=0)

generate

regs: process(load,fifo,data_in)

begin

if load = '1' then


p_fifo(i) <= fifo(i-1);

end loop;

p_fifo (0) <= signed (data_in);

else


p_fifo(i) <= fifo(i);

end loop;

end if;

end process regs;

firstruct: process (fifo)

variable prod: signed (26 downto 0);


ANEXOS 132



begin

idata_tmp := (others => '0');


prod := fifo(i) * coef_rom_b(i);

if (prod(26)='1') then

prod:=prod+255; --redondeo

end if;

idata_tmp := idata_tmp + (prod(26)&prod(26 downto

8));

end loop;

if idata_tmp(19 downto 18) = "01" then --

significa que desborda por arriba


elsif idata_tmp(19 downto 18) = "10" then -

-significa que desborda por abajo


else


end if;

-- end loop;



end generate;

-- ultima_etapa<=std_logic_vector(fifo(10));

ultima_etapa <= (others =>'0');

end a_fir;

ANEXOS 133


9.- Componente RegSimple y RegTMR.

Ficheros igual que en el caso de IIR.

10.-Test Bench para el filtro IIR. (fichero vg_TB_fir.vhd)

-- ADDED BY THE FTUNSHADES PROJECT -------------

-- THIS FILE HAS BEEN MODIFIED TO GENERATE THE TEST

VECTORS;

--GenerateTVG V2.0

-- FT UNSHADES TEAM: J. Tombs, M. Aguirre, V. Baena, F.

Munoz;

----------------------------


LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE STD.TEXTIO.ALL;

----------------------------

-----------------------------------------------------------

---------------------

-- Company:

-- Engineer:

--

-- Create Date: 12:52:47 01/17/2007

ANEXOS 134


-- Design Name: fir

-- Module Name: C:/Proyectos/FIR_secure/FIR/TB_fir.vhd

-- Project Name: FIR

-- Target Device:

-- Tool versions:

-- Description:

--

-- VHDL Test Bench Created by ISE for module: fir

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes:

-- This testbench has been automatically generated using

types std_logic and

-- std_logic_vector for the ports of the unit under test.

Xilinx recommends

-- that these types always be used for the top-level I/O of

a design in order

-- to guarantee that the testbench will bind correctly to

the post-implementation

-- simulation model.

-----------------------------------------------------------

---------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_signed.all;

--USE ieee.numeric_std.ALL;

USE std.textio.all;

ANEXOS 135


USE ieee.std_logic_textio.all;

ENTITY TB_fir_vhd IS

END TB_fir_vhd;

ARCHITECTURE behavior OF TB_fir_vhd IS


SIGNAL ftunshades_cont_vectors: natural :=0;

SIGNAL ftunshades_endsim: std_logic :='L';

SIGNAL ftunshades_normalend:std_logic :='0';

SIGNAL ftunshades_remaining_mem: natural := 100;

---------------------------------------------------


SIGNAL ftunshades_cont_mem: natural := 0;

SIGNAL ftunshades_cont_datas: natural := 0;

SIGNAL ftunshades_data1: signed(19 downto 0);

----------------------------------------

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT iir

PORT(

clk : IN std_logic;

reset : IN std_logic;

load : IN std_logic;

data_in : IN std_logic_vector(17 downto 0);

data_out : OUT std_logic_vector(17 downto 0);

ANEXOS 136


ultima_etapa : OUT std_logic_vector(17 downto 0)

);

END COMPONENT;

--Inputs

SIGNAL clk : std_logic := '0';

SIGNAL reset : std_logic := '1';

SIGNAL load : std_logic := '0';

SIGNAL data_in : std_logic_vector(17 downto 0) :=

(others=>'0');

--Outputs

SIGNAL data_out : std_logic_vector(17 downto 0);

SIGNAL ultima_etapa : std_logic_vector(17 downto 0);

--FIcheros

BEGIN


assert (ftunshades_cont_mem<6291452)

report "Memories full"

severity warning;

assert (ftunshades_cont_vectors<2147483647)

report "Too many vectors"

severity warning;

assert (ftunshades_normalend = '0')

report "Succesful test file generation"

severity failure;

----------------------------------------

ANEXOS 137



ftunshades_endsim <= '1' when

(ftunshades_cont_mem>=6291452 or

ftunshades_cont_vectors>=2147483647);

ftunshades_remaining_mem <= (100*(6291456-

ftunshades_cont_mem))/6291456;

----------------------------------------------


process(clk)

file vector_file: text open write_mode is

"ftunshades_memory.dat";

variable dato1: signed(19 downto 0);

variable DataLine: line;

variable dato_integer: integer;

begin

if (reset='1' or reset='H') then

dato1(0):='1';

else

dato1(0):='0';

end if;

if (load='1' or load='H') then

dato1(1):='1';

else

ANEXOS 138


dato1(1):='0';

end if;

if (data_in(17)='1' or data_in(17)='H') then

dato1(2):='1';

else

dato1(2):='0';

end if;


dato1(3):='1';

else

dato1(3):='0';

end if;


dato1(4):='1';

else

dato1(4):='0';

end if;


dato1(5):='1';

else

dato1(5):='0';

end if;


dato1(6):='1';

else

dato1(6):='0';

end if;


dato1(7):='1';

else

dato1(7):='0';

end if;


ANEXOS 139


dato1(8):='1';

else

dato1(8):='0';

end if;


dato1(9):='1';

else

dato1(9):='0';

end if;


dato1(10):='1';

else

dato1(10):='0';

end if;


dato1(11):='1';

else

dato1(11):='0';

end if;


dato1(12):='1';

else

dato1(12):='0';

end if;


dato1(13):='1';

else

dato1(13):='0';

end if;


dato1(14):='1';

else

dato1(14):='0';

ANEXOS 140


end if;


dato1(15):='1';

else

dato1(15):='0';

end if;


dato1(16):='1';

else

dato1(16):='0';

end if;


dato1(17):='1';

else

dato1(17):='0';

end if;


dato1(18):='1';

else

dato1(18):='0';

end if;


dato1(19):='1';

else

dato1(19):='0';

end if;

if(clk='1' and clk'event) then

ftunshades_data1<=dato1;

if(ftunshades_cont_mem<6291456) then

if(ftunshades_cont_datas=0) then

ftunshades_cont_datas <= ftunshades_cont_datas+1;

dato_integer:=20;

write(DataLine,dato_integer);

ANEXOS 141


writeline(vector_file,DataLine);

ftunshades_cont_vectors<=ftunshades_cont_vectors+1;

elsif(ftunshades_data1=dato1 and

ftunshades_cont_datas<65535 and ftunshades_endsim='L') then

ftunshades_cont_datas<=ftunshades_cont_datas+1;


elsif((ftunshades_cont_datas=65535) or

((ftunshades_data1/=dato1) and ftunshades_cont_datas>1) or

ftunshades_endsim='1') then

dato_integer := 1;


write(DataLine,STRING'(" "));

dato_integer := ftunshades_cont_datas;



dato_integer := 0;



dato_integer := conv_integer(ftunshades_data1);




ftunshades_cont_mem<=ftunshades_cont_mem+2;

ftunshades_cont_datas<=1;

if (ftunshades_endsim='1') then

dato_integer:=1;



dato_integer:=0;



ANEXOS 142


dato_integer:=1;



dato_integer:=0;



dato_integer :=

conv_integer(ftunshades_cont_vectors);



ftunshades_normalend<='1';

end if;


else

dato_integer := 0;



dato_integer := conv_integer(ftunshades_data1);




ftunshades_cont_mem<=ftunshades_cont_mem+1;

ftunshades_cont_datas<=1;

if (ftunshades_endsim='1') then

dato_integer:=1;



dato_integer:=0;



dato_integer:=1;


ANEXOS 143



dato_integer:=0;



dato_integer :=

conv_integer(ftunshades_cont_vectors);



ftunshades_normalend<='1';

end if;


end if;

end if;

end if;

end process;

----------------------------

-- Instantiate the Unit Under Test (UUT)

uut: iir PORT MAP(

clk => clk,

reset => reset,

load => load,

data_in => data_in,

data_out => data_out,

ultima_etapa => ultima_etapa

);

clk <= not clk after 50 ns;

tb : PROCESS

ANEXOS 144


FILE infile: TEXT is IN "entradafir.txt";

FILE outfile: TEXT is OUT "ficherodesalida.txt";

VARIABLE lineaent,lineasal: LINE;

VARIABLE aux:std_logic_vector(17 downto 0);

VARIABLE auxi:integer;

BEGIN

WAIT FOR 100 ns;

reset <='0';

WHile not(ENDFILE(infile))LOOP

READLINE(infile,lineaent);-- LEE UNA LINEA DEL

FICHERO DE ENTRADA

READ(lineaent,auxi);

auxi:=auxi;

aux:= conv_std_logic_vector(auxi,18);

data_in<=aux;

load<='1';

wait for 100 ns;

auxi:=conv_integer(data_out);

WRITE(lineasal,auxi);

WRITE(lineasal,' ');

WRITE(lineasal,ultima_etapa);

writeline(outfile,lineasal);

load<='0';

wait for 200 ns;

END LOOP;

ftunshades_endsim<='1';

wait;

END PROCESS;

END behavior;

ANEXOS 145


DOCUMENTACIÓN

HERRAMIENTA DE TEST: FT-UNSHADES

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