Download - FaMAF - Clase Vhdl Leccion 03
![Page 1: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/1.jpg)
Clase VHDL Lección 03
• Lección 2: Tipos de Datos
– 2_1 - Tipos Predefinidos– 2_2 – Tipos definidos por el usuario– 2_3 - Subtipos– 2_4 - Arrays– 2_5 - Port Arrays– 2_6 - Records– 2_7 - Signed y Unsigned– 2_8 – Conversión de Datos
![Page 2: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/2.jpg)
2_1 Tipos Predefinidos 1/8
![Page 3: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/3.jpg)
2_1 Tipos Predefinidos 2/8
BIT Y BIT_VECTOR: DOS NIVELES LÓGICOS: ‘0’ Y ‘1’SIGNAL X: BIT;SIGNAL Y: BIT_VECTOR(3 DOWNTO 0);SIGNAL W: BIT_VECTOR(0 TO 7);X <= ‘1’;X <= ‘0’;Y <= “0111”;W <= “01110001”;
![Page 4: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/4.jpg)
2_1 Tipos Predefinidos 3/8
STD_LOGIC y STD_LOGIC_VECTOR: OCHO NIVELES:
‘X’ Forcing Unkown (Unkown Sintetizable)‘1’ Forcing High (‘1’ lógico Sintetizable)‘0’ Forcing low (‘0’ lógico Sintetizable)‘Z’ High Impedance (Alta impedancia Sintetizable)‘W’ Weak Unkown‘L’ Weak Low‘H’ Weak High‘-’ Don’t Care
![Page 5: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/5.jpg)
2_1 Tipos Predefinidos 4/8
SIGNAL X: STD_LOGIC;
SIGNAL Y: STD_LOGIC_VECTOR(3 DOWNTO 0) :=“0001”;
SIGNAL W: STD_LOGIC_VECTOR (0 TO 7);
X <= ‘1’;
X <= ‘Z’;
W <= “01110001”;
![Page 6: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/6.jpg)
2_1 Tipos Predefinidos 5/8
Figura: Resolución de múltìples dirvers
![Page 7: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/7.jpg)
2_1 Tipos Predefinidos 6/8STD_ULOGIC y STD_ULOGIC_VECTOR: NUEVE NIVELES: (“Agrega el ‘U’: Unresolved”)
‘X’ Forcing Unkown (Unkown Sintetizable)‘1’ Forcing High (‘1’ lógico Sintetizable)‘0’ Forcing low (‘0’ lógico Sintetizable)‘Z’ High Impedance (Alta impedancia Sintetizable)‘W’ Weak Unkown‘L’ Weak Low‘H’ Weak High‘-’ Don’t Care‘U’ Unresolved
![Page 8: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/8.jpg)
2_1 Tipos Predefinidos 7/8
• BOOLEAN: TRUE O FALSE
• INTEGER: 32 BITS CON SIGNO
• NATURAL: 31 BITS SIN SIGNO
• REAL: +/- 1 10E +/- 38 (NO SINTETIZABLE)
• SIGNED Y UNSIGNED: DEL PAQUETE STD_LOGIC_ARITH DE LA LIBRERÍA IEEE, SIMILARES A LOS STD_LOGIC_VECTORS, PERO ACEPTA OPERACIONES ARITMÉTICAS, TÍPICAS DE LOS ENTEROS.
![Page 9: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/9.jpg)
2_1 Tipos Predefinidos 8/8
Figura: Ejemplos de asignaciones lícitas e ilícitas con distintos tipos de datos
![Page 10: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/10.jpg)
VHDL - Clase Número 1
• Lección 2: Tipos de Datos
– 2_1 - Tipos Predefinidos – 2_2 – Tipos definidos por el usuario– 2_3 - Subtipos– 2_4 - Arrays– 2_5 - Port Arrays– 2_6 - Records– 2_7 - Signed y Unsigned– 2_8 – Conversión de Datos
![Page 11: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/11.jpg)
3_2 Tipos Definidos por el usuario 1/3
![Page 12: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/12.jpg)
3_2 Tipos Definidos por el usuario 2/3
![Page 13: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/13.jpg)
3_2 Tipos Definidos por el usuario 3/3
![Page 14: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/14.jpg)
3_3 Subtipos 1/3
![Page 15: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/15.jpg)
3_3 Subtipos 2/3
![Page 16: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/16.jpg)
3_3 Subtipos 3/3
![Page 17: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/17.jpg)
3_4 Arrays 1/7
![Page 18: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/18.jpg)
3_4 Arrays 2/7
![Page 19: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/19.jpg)
3_4 Arrays 3/7
![Page 20: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/20.jpg)
3_4 Arrays 4/7
![Page 21: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/21.jpg)
3_4 Arrays 5/7
![Page 22: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/22.jpg)
3_4 Arrays 6/7
![Page 23: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/23.jpg)
3_4 Arrays 7/7
![Page 24: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/24.jpg)
3_5 Port Arrays 1/3
![Page 25: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/25.jpg)
3_5 Port Arrays 2/3
![Page 26: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/26.jpg)
3_5 Port Arrays 3/3
![Page 27: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/27.jpg)
3_6 Records 1/1
![Page 28: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/28.jpg)
3_6 R ecords 1/1
![Page 29: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/29.jpg)
3_7 Tipos de Datos Signed y Unsigned 1/3
![Page 30: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/30.jpg)
3_7 Tipos de Datos Signed y Unsigned 2/3
![Page 31: FaMAF - Clase Vhdl Leccion 03](https://reader035.vdocumento.com/reader035/viewer/2022062220/5561afd1d8b42ad9538b5866/html5/thumbnails/31.jpg)
3_7 Tipos de Datos Signed y Unsigned 3/3