diseño digital
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Estado solidoTRANSCRIPT
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Sea U el universo de preguntas. Sea T subconjunto de U, tal que T es
el conjunto de preguntas tontas.
Axioma: T = { Ø }
Copyright © 2007 Elsevier 1-<1>
“No existen preguntas tontas; lo tonto es pensar que alguna
pregunta es tonta, pues CUALQUIER pregunta puede ser
utilizada para dar origen a una discusión genial si se es
suficientemente inteligente”
Carlos A. Esquit
Junio 2010
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Chapter 1 :: From Zero to One
Digital Design and Computer Architecture
Copyright © 2007 Elsevier 1-<2>
Digital Design and Computer Architecture
David Money Harris and Sarah L. Harris
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Chapter 1 :: Topics
• Background
• The Game Plan
• The Art of Managing Complexity
• The Digital Abstraction
• Number Systems
Copyright © 2007 Elsevier 1-<3>
• Number Systems
• Logic Gates
• Logic Levels
• CMOS Transistors
• Power Consumption
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Background
• Microprocessors have revolutionized our world
– Cell phones, Internet, rapid advances in medicine, etc.
• The semiconductor industry has grown from $21
billion in 1985 to $300 billion in 2010
Copyright © 2007 Elsevier 1-<4>
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The Game Plan
• The purpose of this course is that you:
– Learn the principles of digital design
– Learn to systematically design and debug increasingly
complex designs
Copyright © 2007 Elsevier 1-<5>
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The Art of Managing Complexity
• Abstraction
• The Three –Y’s
– Hierarchy
– Modularity
– Regularity
Copyright © 2007 Elsevier 1-<6>
– Regularity
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Abstraction
• Hiding details when
they aren’t important
Micro-
architecture
Architecture
Operating
Systems
Application
Software
datapaths
controllers
instructions
registers
device drivers
programs
focus o
f th
is c
ours
e
Copyright © 2007 Elsevier 1-<7>
Physics
Devices
Analog
Circuits
Digital
Circuits
Logic
electrons
transistors
diodes
amplifiers
filters
AND gates
NOT gates
adders
memories
focus o
f th
is c
ours
e
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The Three -Y’s
• Hierarchy
– A system divided into modules and submodules
• Modularity
– Having well-defined functions and interfaces
Copyright © 2007 Elsevier 1-<8>
• Regularity
– Encouraging uniformity, so modules can be easily
reused
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Example: Flintlock Rifle
• Hierarchy
– Three main modules:
lock, stock, and
barrel
– Submodules of lock:
Copyright © 2007 Elsevier 1-<9>
– Submodules of lock:
hammer, flint,
frizzen, etc.
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Example: Flintlock Rifle
• Modularity
– Function of stock:
mount barrel and
lock
– Interface of stock:
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– Interface of stock:
length and location
of mounting pins
• Regularity
– Interchangeable
parts
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The Digital Abstraction
• Most physical variables are continuous, for
example
– Voltage on a wire
– Frequency of an oscillation
– Position of a mass
Copyright © 2007 Elsevier 1-<11>
– Position of a mass
• Instead of considering all values, the digital
abstraction considers only a discrete subset of
values
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The Analytical Engine
• Designed by Charles Babbage from 1834 –1871
• Considered to be the first digital computer
• Built from mechanical
Copyright © 2007 Elsevier 1-<12>
• Built from mechanical gears, where each gear represented a discrete value (0-9)
• Babbage died before it was finished
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Digital Discipline: Binary Values
• Typically consider only two discrete values:
– 1’s and 0’s
– 1, TRUE, HIGH
– 0, FALSE, LOW
• 1 and 0 can be represented by specific voltage
Copyright © 2007 Elsevier 1-<13>
• 1 and 0 can be represented by specific voltage
levels, rotating gears, fluid levels, etc.
• Digital circuits usually depend on specific voltage
levels to represent 1 and 0
• Bit: Binary digit
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• Decimal numbers
Number Systems
537410
=
10's
colu
mn
100's
colu
mn
1000's
colu
mn
1's
colu
mn
Copyright © 2007 Elsevier 1-<14>
• Binary numbers
11012 =
2's
colu
mn
4's
colu
mn
8's
colu
mn
1's
colu
mn
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• Decimal numbers
Number Systems
537410
= 5 × 103 + 3 × 102 + 7 × 101 + 4 × 100
five
10's
colu
mn
100's
colu
mn
1000's
colu
mn
three seven four
1's
colu
mn
Copyright © 2007 Elsevier 1-<15>
• Binary numbers
five
thousands
three
hundreds
seven
tens
four
ones
11012 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 = 13
10one
eight
2's
colu
mn
4's
colu
mn
8's
colu
mn
one
four
no
two
one
one
1's
colu
mn
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• 20 =
• 21 =
• 22 =
• 23 =
Powers of Two
• 28 =
• 29 =
• 210 =
• 211 =
Copyright © 2007 Elsevier 1-<16>
• 24 =
• 25 =
• 26 =
• 27 =
• 212 =
• 213 =
• 214 =
• 215 =
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• 20 = 1
• 21 = 2
• 22 = 4
• 23 = 8
Powers of Two
• 28 = 256
• 29 = 512
• 210 = 1024
• 211 = 2048
Copyright © 2007 Elsevier 1-<17>
• 24 = 16
• 25 = 32
• 26 = 64
• 27 = 128
• Handy to memorize up to 210
• 212 = 4096
• 213 = 8192
• 214 = 16384
• 215 = 32768
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• Binary to Decimal conversion:
– Convert 101012 to decimal
Number Conversion
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• Decimal to binary conversion:
– Convert 4710 to binary
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• Binary to decimal conversion:
– Convert 100112 to decimal
– 16×1 + 8×0 + 4×0 + 2×1 + 1×1 = 1910
Number Conversion
Copyright © 2007 Elsevier 1-<19>
• Decimal to binary conversion:
– Convert 4710 to binary
– 32×1 + 16×0 + 8×1 + 4×1 + 2×1 + 1×1 = 1011112
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Binary Values and Range
• N-digit decimal number
– How many values? 10N
– Range? [0, 10N - 1]
– Example: 3-digit decimal number: • 103 = 1000 possible values
• Range: [0, 999]
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• Range: [0, 999]
• N-bit binary number
– How many values? 2N
– Range: [0, 2N - 1]
– Example: 3-digit binary number:• 23 = 8 possible values
• Range: [0, 7] = [0002 to 1112]
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Hexadecimal Numbers
Hex Digit Decimal Equivalent Binary Equivalent
0 0
1 1
2 2
3 3
4 4
5 5
6 6
Copyright © 2007 Elsevier 1-<21>
6 6
7 7
8 8
9 9
A 10
B 11
C 12
D 13
E 14
F 15
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Hexadecimal Numbers
Hex Digit Decimal Equivalent Binary Equivalent
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
Copyright © 2007 Elsevier 1-<22>
6 6 0110
7 7 0111
8 8 1000
9 9 1001
A 10 1010
B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111
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Hexadecimal Numbers
• Base 16
• Shorthand to write long binary numbers
Copyright © 2007 Elsevier 1-<23>
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• Hexadecimal to binary conversion:
– Convert 4AF16 (also written 0x4AF) to binary
Hexadecimal to Binary Conversion
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• Hexadecimal to decimal conversion:
– Convert 0x4AF to decimal
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• Hexadecimal to binary conversion:
– Convert 4AF16 (also written 0x4AF) to binary
– 0100 1010 11112
Hexadecimal to Binary Conversion
Copyright © 2007 Elsevier 1-<25>
• Hexadecimal to decimal conversion:
– Convert 4AF16 to decimal
– 162×4 + 161×10 + 160×15 = 119910
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Bits, Bytes, Nibbles…
• Bits
• Bytes & Nibbles10010110
byte
10010110least
significant
bit
most
significant
bit
Copyright © 2007 Elsevier 1-<26>
• Bytes
10010110nibble
CEBF9AD7least
significant
byte
most
significant
byte
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Powers of Two
• 210 = 1 kilo ≈ 1000 (1024)
• 220 = 1 mega ≈ 1 million (1,048,576)
• 230 = 1 giga ≈ 1 billion (1,073,741,824)
Copyright © 2007 Elsevier 1-<27>
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Estimating Powers of Two
• What is the value of 224?
• How many values can a 32-bit variable
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represent?
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Estimating Powers of Two
• What is the value of 224?
24 × 220 ≈ 16 million
• How many values can a 32-bit variable
Copyright © 2007 Elsevier 1-<29>
represent?
22 × 230 ≈ 4 billion
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Digitization
Copyright © 2007 Elsevier 1-<30>
Quantization
Error = Q/2
Quantization
Value Q
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• Decimal
Addition
37345168+
8902
carries 11
Copyright © 2007 Elsevier 1-<31>
• Binary
10110011+
1110
11 carries
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• Add the following
4-bit binary
numbers
Binary Addition Examples
10010101+
Copyright © 2007 Elsevier 1-<32>
• Add the following
4-bit binary
numbers
10110110+
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• Add the following
4-bit binary
numbers
Binary Addition Examples
10010101+
1110
1
Copyright © 2007 Elsevier 1-<33>
• Add the following
4-bit binary
numbers
10110110+
10001
111
Overflow!
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Overflow
• Digital systems operate on a fixed number of
bits
• Addition overflows when the result is too big
to fit in the available number of bits
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• See previous example of 11 + 6
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Signed Binary Numbers
• Sign/Magnitude Numbers
• Two’s Complement Numbers
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Sign/Magnitude Numbers
• 1 sign bit, N-1 magnitude bits
• Sign bit is the most significant (left-most) bit
– Positive number: sign bit = 0
– Negative number: sign bit = 1{ }
1
1 2 2 1 0
2
: , , , ,
( 1) 2n
N N
na i
A a a a a a
A a−
− −
−
= − ∑
L
Copyright © 2007 Elsevier 1-<36>
• Example, 4-bit sign/mag representations of ± 6:
+6 =
- 6 =
• Range of an N-bit sign/magnitude number:
1
0
( 1) 2na i
i
i
A a−
=
= − ∑
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Sign/Magnitude Numbers
• 1 sign bit, N-1 magnitude bits
• Sign bit is the most significant (left-most) bit
– Positive number: sign bit = 0
– Negative number: sign bit = 1{ }
1
1 2 2 1 0
2
: , , , ,
( 1) 2n
N N
na i
A a a a a a
A a−
− −
−
= − ∑
L
Copyright © 2007 Elsevier 1-<37>
• Example, 4-bit sign/mag representations of ± 6:
+6 = 0110
- 6 = 1110
• Range of an N-bit sign/magnitude number:
[-(2N-1-1), 2N-1-1]
1
0
( 1) 2na i
i
i
A a−
=
= − ∑
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Sign/Magnitude Numbers
• Problems:
– Addition doesn’t work, for example -6 + 6:
1110
+ 0110
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10100 (wrong!)
– Two representations of 0 (± 0):
1000
0000
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Two’s Complement Numbers
• Don’t have same problems as sign/magnitude
numbers:
– Addition works
– Single representation for 0
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Two’s Complement Numbers
• Same as unsigned binary, but the most
significant bit (msb) has value of -2N-1
( )2
1
1
0
2 2n
n i
n i
i
A a a−
−
−
=
= − +∑
Copyright © 2007 Elsevier 1-<40>
• Most positive 4-bit number:
• Most negative 4-bit number:
• The most significant bit still indicates the sign
(1 = negative, 0 = positive)
• Range of an N-bit two’s comp number:
0i=
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Two’s Complement Numbers
• Same as unsigned binary, but the most
significant bit (msb) has value of -2N-1
( )2
1
1
0
2 2n
n i
n i
i
A a a−
−
−
=
= − +∑
Copyright © 2007 Elsevier 1-<41>
• Most positive 4-bit number: 0111
• Most negative 4-bit number: 1000
• The most significant bit still indicates the sign
(1 = negative, 0 = positive)
• Range of an N-bit two’s comp number:
[-(2N-1), 2N-1-1]
0i=
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“Taking the Two’s Complement”
• Flip the sign of a two’s complement number
• Method:1. Invert the bits
2. Add 1
• Example: Flip the sign of 3 = 0011
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• Example: Flip the sign of 310 = 00112
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“Taking the Two’s Complement”
• Flip the sign of a two’s complement number
• Method:1. Invert the bits
2. Add 1
• Example: Flip the sign of 3 = 0011
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• Example: Flip the sign of 310 = 00112
1. 1100
2. + 1
1101 = -310
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Two’s Complement Examples
• Take the two’s complement of 610 = 01102
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• What is the decimal value of 10012?
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Two’s Complement Examples
• Take the two’s complement of 610 = 01102
1. 1001
2. + 1
10102 = -610
Copyright © 2007 Elsevier 1-<45>
• What is the decimal value of the two’s
complement number 10012?1. 0110
2. + 1
01112 = 710, so 10012 = -710
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• Add 6 + (-6) using two’s complement
numbers
Two’s Complement Addition
+01101010
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• Add -2 + 3 using two’s complement numbers
+11100011
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• Add 6 + (-6) using two’s complement
numbers
Two’s Complement Addition
+01101010
10000
111
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• Add -2 + 3 using two’s complement numbers
10000
+11100011
10001
111
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Increasing Bit Width
• A value can be extended from N bits to M bits
(where M > N) by using:
– Sign-extension
– Zero-extension
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Sign-Extension
• Sign bit is copied into most significant bits.
• Number value remains the same.
• Example 1:
– 4-bit representation of 3 = 0011
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– 4-bit representation of 3 = 0011
– 8-bit sign-extended value: 00000011
• Example 2:
– 4-bit representation of -5 = 1011
– 8-bit sign-extended value: 11111011
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Zero-Extension
• Zeros are copied into most significant bits.
• Value will change for negative numbers.
• Example 1:
– 4-bit value = 0011 = 3
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– 4-bit value = 00112 = 310
– 8-bit zero-extended value: 00000011 = 310
• Example 2:
– 4-bit value = 1011 = -510
– 8-bit zero-extended value: 00001011 = 1110
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Number System Comparison
Number System Range
Unsigned [0, 2N-1]
Sign/Magnitude [-(2N-1-1), 2N-1-1]
Two’s Complement [-2N-1, 2N-1-1]
For example, 4-bit representation:
Copyright © 2007 Elsevier 1-<51>
-8
1000 1001
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Two's Complement
10001001101010111100110111101111
00000001 0010 0011 0100 0101 0110 0111
1000 1001 1010 1011 1100 1101 1110 11110000 0001 0010 0011 0100 0101 0110 0111
Sign/Magnitude
Unsigned
For example, 4-bit representation:
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• Born to working class parents
• Taught himself mathematics and
joined the faculty of Queen’s
College in Ireland.
• Wrote An Investigation of the Laws
of Thought (1854)
George Boole, 1815 - 1864
Copyright © 2007 Elsevier 1-<52>
of Thought (1854)
• Introduced binary variables
• Introduced the three fundamental
logic operations: AND, OR, and
NOT.
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Logic Gates
• Perform logic functions:
– inversion (NOT), AND, OR, NAND, NOR, etc.
• Single-input:
– NOT gate, buffer
• Two-input:
Copyright © 2007 Elsevier 1-<53>
• Two-input:
– AND, OR, XOR, NAND, NOR, XNOR
• Multiple-input
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Single-Input Logic Gates
NOT
Y = A
A Y
A Y
BUF
Y = A
A Y
A Y
Copyright © 2007 Elsevier 1-<54>
A Y0 1
1 0
A Y0 0
1 1
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Single-Input Logic Gates
NOT
Y = A
A Y
A Y
BUF
Y = A
A Y
A Y
Copyright © 2007 Elsevier 1-<55>
A Y0 1
1 0
A Y0 0
1 1
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Two-Input Logic Gates
AND
Y = AB
AB
Y
OR
Y = A + B
AB
Y
Copyright © 2007 Elsevier 1-<56>
A B Y0 0 0
0 1 0
1 0 0
1 1 1
A B Y0 0 0
0 1 1
1 0 1
1 1 1
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Two-Input Logic Gates
AND
Y = AB
AB
Y
OR
Y = A + B
AB
Y
Copyright © 2007 Elsevier 1-<57>
A B Y0 0 0
0 1 0
1 0 0
1 1 1
A B Y0 0 0
0 1 1
1 0 1
1 1 1
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More Two-Input Logic Gates
XNOR
Y = A + B
A B Y0 0
AB
Y
XOR NAND NOR
Y = A + B Y = AB Y = A + B
A B Y0 0 0
A B Y0 0 1
A B Y0 0 1
AB
YAB
YAB
Y
Copyright © 2007 Elsevier 1-<58>
0 0
0 1
1 0
1 1
0 0 0
0 1 1
1 0 1
1 1 0
0 0 1
0 1 1
1 0 1
1 1 0
0 0 1
0 1 0
1 0 0
1 1 0
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More Two-Input Logic Gates
XNOR
Y = A + B
A B Y0 0
AB
Y
XOR NAND NOR
Y = A + B Y = AB Y = A + B
A B Y0 0 0
A B Y0 0 1
A B Y0 0 1
AB
YAB
YAB
Y
1
Copyright © 2007 Elsevier 1-<59>
0 0
0 1
1 0
1 1
0 0 0
0 1 1
1 0 1
1 1 0
0 0 1
0 1 1
1 0 1
1 1 0
0 0 1
0 1 0
1 0 0
1 1 0
1
0
0
1
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Multiple-Input Logic Gates
NOR3
Y = A+B+C
B C Y
AB YC
A
AND4
Y = ABCD
AB YCD
Copyright © 2007 Elsevier 1-<60>
B C Y0 0
0 1
1 0
1 1
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
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Multiple-Input Logic Gates
NOR3
Y = A+B+C
B C Y
AB YC
A
AND4
Y = ABCD
AB YCD
B C YA
Copyright © 2007 Elsevier 1-<61>
B C Y0 0
0 1
1 0
1 1
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
0
0
0
0
0
0
0
• Multi-input XOR: Odd parity
B C Y0 0
0 1
1 0
1 1
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
1
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Logic Levels
• Define discrete voltages to represent 1 and 0
• For example, we could define:
– 0 to be ground or 0 volts
– 1 to be VDD or 5 volts
• What about 4.99 volts? Is that a 0 or a 1?
Copyright © 2007 Elsevier 1-<62>
• What about 4.99 volts? Is that a 0 or a 1?
• What about 3.2 volts?
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Logic Levels
• Define a range of voltages to represent 1 and 0
• Define different ranges for outputs and inputs to
allow for noise in the system
• What is noise?
Copyright © 2007 Elsevier 1-<63>
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What is Noise?
• Anything that degrades the signal
– E.g., resistance, power supply noise, coupling to
neighboring wires, etc.
• Example: a gate (driver) could output a 5 volt
signal but the signal could arrive at the receiver
Copyright © 2007 Elsevier 1-<64>
signal but the signal could arrive at the receiver
with a degraded value, for example, 4.5 volts
Driver ReceiverNoise
5 V 4.5 V
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What is Noise?
• Anything that degrades the signal
– E.g., resistance, power supply noise, coupling to
neighboring wires, etc.
• Example: a gate (driver) could output a 5 volt
signal but, because of resistance in a long wire,
Copyright © 2007 Elsevier 1-<65>
signal but, because of resistance in a long wire,
the signal could arrive at the receiver with a
degraded value, for example, 4.5 volts
Driver ReceiverNoise
5 V 4.5 V
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The Static Discipline
• Given logically valid inputs, every circuit
element must produce logically valid outputs
• Discipline ourselves to use limited ranges of
voltages to represent discrete values
Copyright © 2007 Elsevier 1-<66>
voltages to represent discrete values
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Logic Levels
Driver Receiver
NMH
Input CharacteristicsOutput Characteristics
VO H
VDD
Logic High
Input Range
Logic High
Output Range
Copyright © 2007 Elsevier 1-<67>
Forbidden
Zone
NML
H
VO L
GND
VIH
VIL
Logic Low
Input RangeLogic Low
Output Range
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Noise Margins
Driver Receiver
NMH
Input CharacteristicsOutput Characteristics
VO H
VDD
Logic High
Input Range
Logic High
Output Range
Copyright © 2007 Elsevier 1-<68>
Forbidden
Zone
NML
H
VO L
GND
VIH
VIL
Logic Low
Input RangeLogic Low
Output Range
NMH = VOH – VIH
NML = VIL – VOL
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DC Transfer Characteristics
V(Y)
VOH
VDD
A YV(Y)
VOH
VDD
Ideal Buffer: Real Buffer:
Copyright © 2007 Elsevier 1-<69>
VDD
V(A)VOL
VIL, V
IH
0V
DD
V(A)
VOL
VIL
VIH
Unity Gain
Points
Slope = 1
0V
DD / 2
NMH = NML = VDD/2 NMH , NML < VDD/2
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DC Transfer Characteristics
NMH
Input CharacteristicsOutput CharacteristicsV
DD
VO H
A Y
V(Y)
VOH
VDD
Copyright © 2007 Elsevier 1-<70>
Forbidden
Zone
NML
VO L
GND
VIH
VIL
VDD
V(A)
VOL
VIL
VIH
Unity Gain
Points
Slope = 1
0
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VDD Scaling
• Chips in the 1970’s and 1980’s were designed
using VDD = 5 V
• As technology improved, VDD dropped
– Avoid frying tiny transistors
– Save power
Copyright © 2007 Elsevier 1-<71>
– Save power
• 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …
• Be careful connecting chips with different
supply voltages
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Logic Family Examples
Logic Family VDD VIL VIH VOL VOH
TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4
CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84
Copyright © 2007 Elsevier 1-<72>
LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4
LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7
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Transistors
• Logic gates are usually built out of transistors
• Transistor is a three-ported voltage-controlled switch
– Two of the ports are connected depending on the voltage
on the third port
– For example, in the switch below the two terminals (d and
Copyright © 2007 Elsevier 1-<73>
– For example, in the switch below the two terminals (d and
s) are connected (ON) only when the third terminal (g) is 1
g
s
d
g = 0
s
d
g = 1
s
d
OFF ON
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Robert Noyce, 1927 - 1990
• Nicknamed “Mayor of Silicon
Valley”
• Cofounded Fairchild
Semiconductor in 1957
• Cofounded Intel in 1968
Copyright © 2007 Elsevier 1-<74>
• Cofounded Intel in 1968
• Co-invented the integrated circuit
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Silicon
• Transistors are built out of silicon, a semiconductor
• Pure silicon is a poor conductor (no free charges)
• Doped silicon is a good conductor (free charges)
– n-type (free negative charges, electrons)
– p-type (free positive charges, holes)
Copyright © 2007 Elsevier 1-<75>
Silicon Lattice
Si SiSi
Si SiSi
Si SiSi
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
Free electron Free hole
n-Type p-Type
– p-type (free positive charges, holes)
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MOS Transistors
gatesource drainPolysilicon
• Metal oxide silicon (MOS) transistors:
– Polysilicon (used to be metal) gate
– Oxide (silicon dioxide) insulator
– Doped silicon
Copyright © 2007 Elsevier 1-<76>
n
p substrate
SiO2
nMOS
Polysilicon
n
gate
source drain
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Transistors: nMOS
gate
source drain gatesource drain
V
Gate = 0, so it is OFF
(no connection between
source and drain)
Gate = 1, so it is ON
(channel between
source and drain)
Copyright © 2007 Elsevier 1-<77>
n
p
gate
substrate
n n
p substrate
n
GND
GND
VDD
GND
+++++++
- - - - - - -
channel
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Transistors: pMOS
• pMOS transistor is just the opposite
– ON when Gate = 0
– OFF when Gate = 1
gatesource drain
Polysilicon
Copyright © 2007 Elsevier 1-<78>
SiO2
n
p p
gate
source drain
substrate
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Transistor Function
g
s
d
g = 0
s
d
g = 1
s
d
nMOS OFFON
Copyright © 2007 Elsevier 1-<79>
g
d
s
d
s
d
s
pMOS ONOFF
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Transistor Function
• nMOS transistors pass good 0’s, so connect source
to GND
• pMOS transistors pass good 1’s, so connect source
to VDD
pMOS
Copyright © 2007 Elsevier 1-<80>
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
CMOS
Circuits
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CMOS Gates: NOT Gate
VDD
A YN1
P1
NOT
Y = A
A Y
A Y
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GND
A Y0 1
1 0
A P1 N1 Y
0
1
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CMOS Gates: NOT Gate
VDD
A YN1
P1
NOT
Y = A
A Y
A Y
Copyright © 2007 Elsevier 1-<82>
GND
A Y0 1
1 0
A P1 N1 Y
0 ON OFF 1
1 OFF ON 0
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CMOS Gates: NAND Gate
A
B
Y
N2
N1
P2 P1NAND
Y = AB
A B Y
AB
Y
Copyright © 2007 Elsevier 1-<83>
A B Y0 0 1
0 1 1
1 0 1
1 1 0 A B P1 P2 N1 N2 Y
0 0
0 1
1 0
1 1
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CMOS Gates: NAND Gate
A
B
Y
N2
N1
P2 P1NAND
Y = AB
A B Y
AB
Y
Copyright © 2007 Elsevier 1-<84>
A B Y0 0 1
0 1 1
1 0 1
1 1 0 A B P1 P2 N1 N2 Y
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
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CMOS Gate Structure
pMOS
pull-up
network
output
inputs
Copyright © 2007 Elsevier 1-<85>
output
nMOS
pull-down
network
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NOR Gate
How do you build a three-input NOR gate?
Copyright © 2007 Elsevier 1-<86>
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NOR3 Gate
Three-input NOR gate
A
Copyright © 2007 Elsevier 1-<87>
B
CY
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Other CMOS Gates
How do you build a two-input AND gate?
Copyright © 2007 Elsevier 1-<88>
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Other CMOS Gates
Two-input AND gate
AY
Copyright © 2007 Elsevier 1-<89>
AB
Y
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Transmission Gates
• nMOS pass 1’s poorly
• pMOS pass 0’s poorly
• Transmission gate is a better switch
– passes both 0 and 1 well
• When EN = 1, the switch is ON:
A B
EN
EN
Copyright © 2007 Elsevier 1-<90>
• When EN = 1, the switch is ON:
– EN = 0 and A is connected to B
• When EN = 0, the switch is OFF:
– A is not connected to B
EN
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Pseudo-nMOS Gates
• Pseudo-nMOS gates replace the pull-up network
with a weak pMOS transistor that is always on
• The pMOS transistor is called weak because it
pulls the output HIGH only when the nMOS
network is not pulling it LOW
Copyright © 2007 Elsevier 1-<91>
network is not pulling it LOW
Y
inputsnMOS
pull-down
network
weak
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Pseudo-nMOS Example
Pseudo-nMOS NOR4
Y
weak
Copyright © 2007 Elsevier 1-<92>
A B
Y
C D
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Gordon Moore, 1929 -
• Cofounded Intel in
1968 with Robert
Noyce.
• Moore’s Law: the
number of transistors
Copyright © 2007 Elsevier 1-<93>
number of transistors
on a computer chip
doubles every year
(observed in 1965)
• Since 1975, transistor
counts have doubled
every two years.
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Moore’s Law
Copyright © 2007 Elsevier 1-<94>
• “If the automobile had followed the same development cycle as the
computer, a Rolls-Royce would today cost $100, get one million miles
to the gallon, and explode once a year . . .”
– Robert Cringley
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Power Consumption
• Power = Energy consumed per unit time
• Two types of power consumption:
– Dynamic power consumption
– Static power consumption
Copyright © 2007 Elsevier 1-<95>
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Dynamic Power Consumption
• Power to charge transistor gate capacitances
• The energy required to charge a capacitance, C, to
VDD is ½ CVDD2
• If the circuit is running at frequency f, and all
transistors switch (from 1 to 0 or vice versa) at
Copyright © 2007 Elsevier 1-<96>
transistors switch (from 1 to 0 or vice versa) at
that frequency, the capacitor is charged Tf times
during a period of time T.
• Thus, the total dynamic power consumption is:
Pdynamic =αCVDD2f
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Static Power Consumption
• Power consumed when no gates are switching
• It is caused by the quiescent supply current, IDD,
also called the leakage current
• Thus, the total static power consumption is:
Copyright © 2007 Elsevier 1-<97>
Pstatic = IDDVDD
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Power Consumption Example
• Estimate the power consumption of a wireless
handheld computer
– VDD = 1.2 V
– C = 20 nF
– f = 1 GHz
Copyright © 2007 Elsevier 1-<98>
– f = 1 GHz
– IDD = 20 mA
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Power Consumption Example
• Estimate the power consumption of a wireless
handheld computer
– VDD = 1.2 V
– C = 20 nF
– f = 1 GHz
Copyright © 2007 Elsevier 1-<99>
– f = 1 GHz
– IDD = 20 mA
P = ½CVDD2f + IDDVDD
= ½(20 nF)(1.2 V)2(1 GHz) +
(20 mA)(1.2 V)
= 14.4 W