colaborativo 2.grupo 6

Escuela de Ciencias Básicas, Tecnología e Ingeniería

Curso: SISTEMAS DIGITALES BASICOS Ingeniería de telecomunicaciones

1

UNUVERSIDAD NACIONAL ABIERTA Y ADISTACIA UNAD

TRABAJO COLABORATIVO No.2

CURSO:

SISTEMAS DIGITALES BASICOS

POR:

SAMUEL QUINTERO CASAS C.C. 820156

CHAPARRO LUIS GERMAN C.C.

ALTAMAR ALEJANDRO ENRIQUE C.C.

DIRECTORA:

MARIELA MARQUEZ

22/05/12

COLOMBIA



2

INTRODUCCION

El siguiente trabajo se realiza con el fin de implementar el diseño del multiplexor

propuesto en el primer trabajo colaborativo en lenguaje VHDL y conocer todo lo

relacionado con este lenguaje.



3 Diseño del multiplexor

-------------------------------------------------------------------------------

--

-- File : rre.vhd

-- Generated : Fri Nov 13 14:28:28 2011

-- From : interface description file

-- By : Itf2Vhdl ver. 1.20

--

-------------------------------------------------------------------------------

--

-- Description:

--

-------------------------------------------------------------------------------

--{{Section below this comment is automatically maintained

-- And may be overwritten

--{entity {e} architecture {r}}

Library IEEE;

Use IEEE.STD_LOGIC_1164.all;

Entity e is



4 Port (

d0: in STD_LOGIC;

d1: in STD_LOGIC;

d2: in STD_LOGIC;

d3: in STD_LOGIC;

s1: in STD_LOGIC;

s0: in STD_LOGIC;

q0: out STD_LOGIC;

q1: out STD_LOGIC;

q2: out STD_LOGIC;

q3: out STD_LOGIC;

a0: in STD_LOGIC;

a1: in STD_LOGIC;

a2: in STD_LOGIC;

a3: in STD_LOGIC;

c0: in STD_LOGIC;

c1: in STD_LOGIC;

c2: in STD_LOGIC;

c3: in STD_LOGIC;

b0: in STD_LOGIC;

b1: in STD_LOGIC;

b2: in STD_LOGIC;



5 b3: in STD_LOGIC

);

End e;

--}} End of automatically maintained section

Architecture r of e is

Begin

q0<=(a0 and not s1 and not s0) or

(a1 and not s1 and s0)or

(a2 and s1 and not s0) or

(a3 and s1 and s0);

q1<=(b0 and not s1 and not s0) or

(b1 and not s1 and s0)or

(b2 and s1 and not s0) or

(b3 and s1 and s0);

q2<=(c0 and not s1 and not s0) or

(c1 and not s1 and s0)or

(c2 and s1 and not s0) or

(c3 and s1 and s0);



6

q3<=(d0 and not s1 and not s0) or

(d1 and not s1 and s0)or

(d2 and s1 and not s0) or

(d3 and s1 and s0);

-- enter your statements here --

end r;

SIMULACION DEL MULTIPLEXOR



7 SEGUNDA ACTIVIDAD

Tomando como entradas d0,d1,d2,d3

Tomando como selectores s

Tomando como salida q

Usando el condicional if

Código fuente

-------------------------------------------------------------------------------

--

-- File : rre.vhd




--

-------------------------------------------------------------------------------

--

-- Description :

--

-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained



8 -- and may be overwritten


library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity e is

port(

d0 : in STD_LOGIC;

d1 : in STD_LOGIC;

d2 : in STD_LOGIC;

d3 : in STD_LOGIC;

s : in STD_LOGIC_VECTOR(1 downto 0);

q : out STD_LOGIC

);

end e;


architecture r of e is

begin

process (d3,d2,d1,d0,s,q)



9

begin if (s="00") then

q<=d0;

elsif(s="01")

then q<=d1;

else (s="10") then

q<=d2;

else q<=d3;

end if;

end process;

end r;



10

2. Usando las expresiones lógicas

Código fuente:

-------------------------------------------------------------------------------

--

-- File : rre.vhd




--

-------------------------------------------------------------------------------

--

-- Description :

--

-------------------------------------------------------------------------------


-- and may be overwritten


library IEEE;



11 use IEEE.STD_LOGIC_1164.all;

entity e is

port(

d0 : in STD_LOGIC;

d1 : in STD_LOGIC;

d2 : in STD_LOGIC;

d3 : in STD_LOGIC;

s1 : in STD_LOGIC;

s0 : in STD_LOGIC;

q0 : out STD_LOGIC

);

end e;



begin

q0<=(d0 and not s1 and not s0) or

(d1 and not s1 and s0)or

(d2 and s1 and not s0) or



12 (d3 and s1 and s0);

-- enter your statements here --

end r;

Se realiza la simulación



13



14

3. Usando la expresión when selector

Código fuente

-------------------------------------------------------------------------------

--

-- File : rre.vhd






15 --

-------------------------------------------------------------------------------

--

-- Description :

--

-------------------------------------------------------------------------------




library IEEE;


entity e is

port(

d0 : in STD_LOGIC;

d1 : in STD_LOGIC;

d2 : in STD_LOGIC;

d3 : in STD_LOGIC;

s : in STD_LOGIC_VECTOR(1 downto 0);

q : out STD_LOGIC



16 );

end e;



begin

with s select

q<= d0 when "00",

d1 when "01",

d2 when "10",

d3 when others;

end r;

Simulación



17

4.

Usando When

Código fuente

-------------------------------------------------------------------------------

--

-- File : rre.vhd




18 -- From : interface description file


--

-------------------------------------------------------------------------------

--

-- Description :

--

-------------------------------------------------------------------------------




library IEEE;


entity e is

port(

d0 : in STD_LOGIC;

d1 : in STD_LOGIC;

d2 : in STD_LOGIC;

d3 : in STD_LOGIC;



19 s : in STD_LOGIC_VECTOR(1 downto 0);

q : out STD_LOGIC

);

end e;



begin

q<= d0 when s="00" else

d1 when s="01" else

d2 when s="10" else

d3 when s="11";

end r;

Simulación

Diseño del multiplexor



20



21

CONCLUSIONES

Con el anterior trabajo se puede ver todo lo que se puede hacer con este

importante programa, por lo que se mostraron varios ejemplo creados en el

lenguaje vhdl.

colaborativo 2.grupo 6

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