ELECTRNICA DIGITAL IMICROPROCESSADORS

(5 Q, Electr. Ind. i Autom.,pla 2009)

Descripcions VHDL idiagrames corresponents

a la part d'aplicacions

Tema I - HDL

Jordi CospTardor 2014

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 2/30

FUNCI Y=X1X2X3

Declaracidelesllibrerieslibraryieee;useieee.std_logic_1164.all;

Definicidel'entitatentityFUNCIOisport(X1:inbit;X2:inbit;X3:inbit;Y:outbit);endFUNCIO;

Descripcidel'arquitecturaarchitectureLOGICofFUNCIOissignalX4:bit;beginY

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 3/30

SEMISUMADOR - ARQUITECTURA LGICA

DeclaracidelesllibrerieslibraryIEEE;useIEEE.std_logic_1164.all;Descripcidel'entitatentityH_ADDERisport(A:inbit;B:inbit;SUM:outbit;CARRY:outbit);endH_ADDER;

Descripcidel'arq.logicaarchitectureLOGICofH_ADDERisbeginSUM

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 4/30

SEMISUMADOR - ARQUITECTURA ESTRUCTURAL

DeclaracidelesllibrerieslibraryIEEE;useIEEE.std_logic_1164.all;Descripcidel'entitatentityH_ADDERisport(A:inbit;B:inbit;SUM:outbit;CARRY:outbit);endH_ADDER;

Descr.del'arq.estructuralarchitectureSTRUCTofH_ADDERis

componentXOR_2port(X,Y:inbit;Z:outbit);endcomponent;

componentAND_2port(X,Y:inbit;Z:outbit);endcomponent;

beginX1:XOR_2portmap(X=>A,Y=>B,Z=>SUM);A1:AND_2portmap(X=>A,Y=>B,Z=>CARRY);endSTRUCT;

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 5/30

SEMISUMADOR - ARQUITECTURA DE COMPORTAMENT

DECLARACIDELESLLIBRERIESlibraryIEEE;useIEEE.std_logic_1164.all;Descripcidel'entitatentityH_ADDERisport(A:inbit;B:inbit;SUM:outbit;CARRY:outbit);endH_ADDER;

DESCR.DEL'ARQ.COMP.architectureBEHofH_ADDERisbegin SUM

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 6/30

SUMADOR COMPLERT - ARQUITECTURA LGICA

DECLARACIDELESLLIBRERIESlibraryIEEE;useIEEE.std_logic_1164.all;

Descripcidel'entitatentityF_ADDERisport(A,B,CIN:inbit;SUM,COUT:outbit);endF_ADDER;

DESCR.DEL'ARQ.LGICAarchitectureLOGICofF_ADDERisbeginSUM

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 7/30

SUMADOR COMPLERT - ARQUITECTURA ESTRUCTURAL

DECLARACIDELESLLIBRERIESlibraryIEEE;useIEEE.std_logic_1164.all;

Descripcidel'entitatentityF_ADDERisport(A,B,CIN:inbit;SUM,COUT:outbit);ENDF_ADDER;

DESCRIPCIDEL'ARQ.ESTRUCTURALarchitectureSTRUCTUREofF_ADDERiscomponentXOR_2port(X,Y:inbit;Z:outbit);endcomponent;componentAND_2port(X,Y:inbit;Z:outbit);endcomponent;componentOR_2port(X,Y:inbit;Z:outbit);endcomponent;signalD,E,F:bit;

BEGINX1:XOR_2portmap(X=>A,Y=>B,Z=>D);X2:XOR_2portmap(X=>D,Y=>CIN,Z=>SUM);A1:AND_2portmap(X=>D,Y=>CIN,Z=>E);A2:AND_2portmap(X=>A,Y=>B,Z=>F);O1:OR_2portmap(X=>E,Y=>F,Z=>COUT);endSTRUCTURE;

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 8/30

SUMADOR COMPLERT - ARQUITECTURA DE COMPORTAMENT

DECLARACIDELESLLIBRERIESlibraryIEEE;useIEEE.std_logic_1164.all;

Descripcidel'entitatentityF_ADDERisport(A,B,CIN:inbit;SUM,COUT:outbit);ENDF_ADDER;

DESCRIPCIDEL'ARQ.PERCOMPORT.architectureBEHofF_ADDERisbeginSUM

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 9/30

CIRCUIT INTEGRAT 74153 - MUX 4X1 DUAL

libraryieee;useieee.std_logic_1164.all;

entityLS153isPort(A:instd_logic;B:instd_logic;C:instd_logic_vector(3downto0);CC:instd_logic_vector(3downto0);G:instd_logic;GG:instd_logic;Y:outstd_logic;YY:outstd_logic);endLS153;

architectureBEHofLS153issignalS,SS:std_logic_vector(2downto0);beginS

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 10/30

CIRCUIT INTEGRAT 7442 - DESCOD. BCD - WHEN/ELSE

libraryieee;useieee.std_logic_1164.all;

entityLS42isport(A:instd_logic_vector(3downto0);O:outstd_logic_vector(9downto0));

endLS42;

architectureBEHAVIORALofLS42isbeginO

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 11/30

CIRCUIT INTEGRAT 7442 - DESCOD. BCD - WITH/SELECT

libraryieee;useieee.std_logic_1164.all;

entityLS42isport(A:instd_logic_vector(3downto0);O:outstd_logic_vector(9downto0));

endLS42;

architectureBEHAVIORAL2ofLS42isbeginwithAselectO

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 12/30

SUMADOR COMPLERT S DE VARIABLES

process(A,B,Cin)variableD,E,F:std_logic;beginD:=AxorB;SUM

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 13/30

MUX 4x1 - IF

PROCESS(SEL,I)beginif(SEL=00)thenO

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 14/30

MUX 4x1 - CASE

process(SEL,I)begincaseSELiswhen00=>OOOO

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 15/30

CIRCUIT INTEGRAT 7442 - DESCOD. BCD - IF

libraryieee;useieee.std_logic_1164.all;

entityLS42isport(A:instd_logic_vector(3downto0);O:outstd_logic_vector(9downto0));

endLS42;

architectureBEH_IFofLS42isbeginprocess(A)beginifA="0000"thenO

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 16/30

CIRCUIT INTEGRAT 7442 - DESCOD. BCD - CASE

libraryieee;useieee.std_logic_1164.all;

entityLS42isport(A:instd_logic_vector(3downto0);O:outstd_logic_vector(9downto0));

endLS42;

architectureBEH_CASEofLS42isbeginprocess(A)begincaseAiswhen"0000"=>O

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 17/30

LATCH SR

libraryieee;useieee.std_logic_1164.all;

entitySRLATCHisport(Sn,Rn:instd_logic;Q,Qn:outstd_logic);endSRLATCH;

architectureBEHofSRLATCHissignalQ_AUX,Qn_AUX:std_logic;beginQ_AUX

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 18/30

BIESTABLE D AMB RESET SNCRON

libraryieee;useieee.std_logic_1164.all;

entityDFFport(CLK,RST,D:instd_logic;Q:outstd_logic);endDFF;

architectureBEHofDFFisbeginprocess(CLK)beginif(CLK='1'andCLK'event)thenif(RST='1')thenQ

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 19/30

BIESTABLE D AMB RESET ASNCRON

libraryieee;useieee.std_logic_1164.all;

entityDFFport(CLK,RST,D:instd_logic;Q:outstd_logic);endDFF;

architectureBEHAVIORALASINCofDFFisbeginprocess(CLK,RST)beginif(RST='1')thenQ

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 20/30

BIESTABLE JK AMB RESET SNCRON

libraryieee;useieee.std_logic_1164.all;

entityJKFFisPort(CLK,RST,J,K:instd_logic;Q,Qn:outstd_logic);endJKFF;

architectureBEHAVIORALofJKFFissignalQ_aux:std_logic;

beginQ

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 21/30

COMPTADOR SNCRON - ESTRUCTURAL

libraryieee;useieee.std_logic_1164.all;

entityCOMPTADOR_4isport(CLK,RST,ENABLE:instd_logic;Q:outstd_logic_vector(3downto0));endCOMPTADOR_4;

architectureSTRUCTURALofCOMPTADOR_4iscomponentTFFisport(CLK,RST,T:instd_logic;Q:outstd_logic);endcomponent;

signalC:std_logic_vector(3downto0);signalEN:std_logic_vector(3downto0);beginEN(0)CLK,RST=>RST,T=>EN(1),Q=>C(1));TFF2:TFFportmap(CLK=>CLK,RST=>RST,T=>EN(2),Q=>C(2));TFF3:TFFportmap(CLK=>CLK,RST=>RST,T=>EN(3),Q=>C(3));endSTRUCTRAL;

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 22/30

COMPTADOR SNCRON - COMPORTAMENT

libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;

entityCOMPTADOR_4isport(CLK,RST,ENABLE:instd_logic;Q:outstd_logic_vector(3downto0));endCOMPTADOR_4;

architectureBEHAVIORALofCOMPTADOR_4issignalTMP:std_logic_vector(3downto0);beginprocess(CLK)beginif(CLK'eventandCLK='1')thenif(RST='1')thenTMP

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 23/30

SHIFT REGISTER ESTRUCTURAL

libraryieee;useieee.std_logic_1164.all;

entitySHIFT_1x4isport(SR_IN,ENABLE,CLK:instd_logic;SR_OUT:outstd_logic);endSHIFT_1X4;

architectureSTRUCTURALofSHIFT_1X4iscomponentDFFport(CLK,E,D:instd_logic;Q:outstd_logic);endcomponent;signalSR:std_logic_vector(4downto0);beginSR(0)ENABLE,D=>SR(0),Q=>SR(1));DFF1:DFFportmap(CLK=>CLK,E=>ENABLE,D=>SR(1),Q=>SR(2));DFF2:DFFportmap(CLK=>CLK,E=>ENABLE,D=>SR(2),Q=>SR(3));DFF3:DFFportmap(CLK=>CLK,E=>ENABLE,D=>SR(3),Q=>SR(4));endSTRUCTURAL;

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 24/30

SHIFT REGISTER ESTRUCTURAL - FOR

libraryieee;useieee.std_logic_1164.all;

entitySHIFT_1x4isport(SR_IN,ENABLE,CLK:instd_logic;SR_OUT:outstd_logic);endSHIFT_1X4;

architectureSTRUCTURALofSHIFT_1X4iscomponentDFFport(CLK,E,D:instd_logic;Q:outstd_logic);endcomponent;signalSR:std_logic_vector(4downto0);beginSR(0)ENABLE,D=>SR(I),Q=>SR(I+1));endgenerate;endSTRUCTURAL;

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 25/30

SHIFT REGISTER COMPORTAMENT

libraryieee;useieee.std_logic_1164.all;

entitySHIFT_1x4isport(SR_IN,ENABLE,CLK:instd_logic;SR_OUT:outstd_logic);endSHIFT_1X4;

architectureBEHAVIORALofSHIFT_1X4issignalSR:std_logic_vector(4downto0);beginSR(0)

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 26/30

CALCULADOR DE PARITAT

process(X)variableTEMP:std_logic;

beginTEMP:='0';forIin3downto0loopTEMP:=TEMPxorX(i);endloop;P

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 27/30

TESTBENCH

libraryieee;useieee.std_logic_1164.all;

entityTBisendTB;

architectureBEHAVIORofTBiscomponentTESTport(CLK:instd_logic;RESET:instd_logic;COUNT:outstd_logic_vector(3downto0));endcomponent;signalCLK:std_logic:='0';signalRESET:std_logic:='0';signalCOUNT:std_logic_vector(3downto0);constantCLK_PERIOD:time:=10ns;beginUUT:TESTportmap(CLK=>CLK,COUNT=>COUNT,RESET=>RESET);CLK_PROCESS:processbeginCLK

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 28/30

MQUINA D'ESTATS 1 PROCESS

libraryieee;useieee.std_logic_1164.all;

entityFSMisport(CLK,RST,X1:instd_logic;

OUTP:outstd_logic);endFSM;

architectureBEHofFSMistypeTIPUSis(S1,S2,S3,S4);signalESTAT:TIPUS;

beginprocess(CLK)begin

if(CLK=1andCLKevent)thenif(RST=1)then

ESTAT

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 29/30

MQUINA D'ESTATS 3 PROCESS

libraryieee;useieee.std_logic_1164.all;

entityFSMisport(CLK,RST,X1:instd_logic;

OUTP:outstd_logic);endFSM;

architectureBEHofFSMistypeTIPUSis(S1,S2,S3,S4);signalESTAT,ESTAT_SEG:TIPUS;

beginEstabliml'estat(proc.seqencial)PROCESS1:process(CLK)begin

if(CLK=1andCLKevent)thenif(RST=1)then

ESTAT

Electr. Dig. i P. 5 Q, E.I.A., pla 2009 Descripcions VHDL i diagrames Tema I p. 30/30

Sortidessegonsestat(proc.Comb.)

PROCESS3:process(ESTAT)begin

caseESTATiswhenS1=>

OUTP

OUTP

OUTP

OUTP