tema 4 lecciones
DESCRIPTION
sistemas digitalesTRANSCRIPT
BLOQUES ARITMÉTICOS4 .1
Elena ValderramaUniversidad Autónoma de Barcelona
1. SUMA
2. RESTA
3. MULTIPLICACIÓN
4. DIVISIÓN
Los bloques aritméticos constituyen una parte importante en caso cualquier circuito
digital.
Estudiaremos circuitos capaces de implementar las 4 operaciones básicas:
4 .1
2
1. Suma binaria
Sumador paralelo: Ver lecciones 2.2 y 2.3 de la semana 2.
Sumador
1 bit
xi yi
acarreoINacarreoOUT
zi
Sumador
1 bit
xn-1 yn-1
acarreoOUT
zn-1
Sumador
1 bit
zn-2
Sumador
1 bit
x1 y1
z1
Sumador
1 bit
x0 y0
acarreoIN
z0
…
xn-2 yn-2
Sumador
n bits
Sumador
n bits�
�
�
n
nn+1
acarreo01
4 .1
Full_Adder (FA)
3
2. Resta binaria
Un restador binario realiza el cálculo:
Restador
n bits
Restador
n bits�
�
�
n
nn+1
acarreo01
� � � � � � �����
donde:
� � ��� ���… � �
� � ��������…����
acarreo0: 1 bit
(habitualmente igual a 0)
�2�≤��2� � 1
4 .1
¿Cómo representamos un número negativo?
Si D<0, D se representa por un número de n+1
bits llamado el “complemento a 2” de D:
� � ���.2� �����.2
��������.2����⋯� ��. 2 � ��
4
2. Resta binaria
Algoritmo “manual”:
n pasos, en cada paso calculamos:
4 .1
� El bit “resta”:
� El acarreo hacia la etapa
siguiente:
1 1 0 0 1 0 0 1
1 0 0 1 1 1 0 0
�� � � �-��-���������2
������� � 1 ⟺
� �-��-������ ! 0
5
Algoritmo-1 de la resta
acarreo(0) <= acarreo_inicial; -- (habitualmente 0)
for i in 0 to n-1 loop
d(i) <= (x(i) + y(i) + acarreo(i)) mod 2;
acarreo(i+1) <= sign(x(i) - y(i) - acarreo(i));
end loop;
s(n) <= acarreo(n);
Algoritmo-2 de la resta
acarreo(0) <= acarreo_inical; ; -- (habitualmente 0)
for i in 0 to n-1 loop
d(i) <= x(i) xor y(i) xor acarreo(i);
acarreo(i+1) <=
(not(x(i)) and y(i)) or (not(x(i)) and acarreo(i))
or (y(i) and acarreo(i));
end loop;
s(n) <= acarreo(n);
4 .12. Resta binaria
� � # � � ���2 � � � # � � ���2
6
� d(i) <= x(i) xor y(i) xor acarreo(i);
� acarreo(i+1) <=
(not(x(i)) and y(i)) or (not(x(i)) and acarreo(i))
or (y(i) and acarreo(i))
4 .12. Resta binaria
FS
xn-1 yn-1
dn=acarreoOUT
dn-1
FS
dn-2
FS
x1 y1
d1
FS
x0 y0
acarreoIN
d0
…
xn-2 yn-2
Restador
n bits
Restador
n bits�
�
�
n
nn+1
acarreo01
Full_Substractor(FS)
Restador
1 bit
xi yi
acarreoINacarreoOUT
di
7
(Ejercicio)
Construir un circuito que calcule D = x - y (x, y de n bits) y devuelva el valor de D en la
representación clásica de “signo y magnitud”, es decir, como D = (-1)sign·|D|
Sugerencia: Calcula en paralelo x – y and y– x y selecciona el |D| dependiendo del signo de x – y.
4 .1
8
(Solución del ejercicio)
Construir un circuito que calcule D = x - y (x, y de n bits) y devuelva el valor de D en la
representación clásica de “signo y magnitud”, es decir, como D = (-1)sign·|D|
Sugerencia: Calcula en paralelo X – Y and Y – X y selecciona el |D| dependiendo del signo de X – Y.
4 .1
x y
subtract. 0
y x
subtract. 0
10
d’ d’’
dsign
Restador Restador
9
Algoritmo1:
p0 = X·y0;
p1 = X·y1·2;
p2 = X·y2·22;
···
pm-1 = X·ym-1·2m-1;
P = p0 + p1 + p2 + ··· + pm-1 .
4 .13. Multiplicador binario
Un multiplicador realiza el cálculo:
$ � �. �
donde:
� � ��� ���… � �
� � �%���%��…����
Mayor valor de P:
2� � 1 . 2% � 1 � 2��% � 2� �
�2% � 1 ! 2��%
⇒ P es un número de n+m bits
� � �%��. 2%��
+�%�� . 2%��+…+��. 2+��
$ � �. �%��. 2%��
+�. �%�� . 2%��+…+�. ��. 2+�. ��
10
Ejemplo:
101101
x 1011
---------
101101 → p0
101101 → p1
000000 → p2
101101 → p3
------------------
111101111 → P
4 .13. Multiplicador binario
Algoritmo1:
p0 = X·y0;
p1 = X·y1·2;
p2 = X·y2·22;
···
pm-1 = X·ym-1·2m-1;
P = p0 + p1 + p2 + ··· + pm-1 .
11
Algoritmo2: “Right-to left algorithm”
acc <= 0;
for i in 0 to m-1 loop
acc <= acc + X*(2**i)*y(i);
end loop;
P <= acc;
0 X
acc_in X
y
acc_out
y(0)
X·2
acc_in X
y
acc_out
y(1)
X·22
acc_in X
y
acc_out
y(2)
X·2m-1
acc_in X
y
acc_out
y(m-1)
P
····
acc_in
adder
X
acc_out
y
4 .13. Multiplicador binario
p0 = X·y0;
p1 = X·y1·2;
p2 = X·y2·22;
···
pm-1 = X·ym-1·2m-1;
P = p0 + p1 + p2 + ··· + pm-1 .
12
Definición equivalente:
Calcular Q,R tal que X/Y = Q +R/Y,
donde Q es un múltiplo de 2�& ,
sabiendo que el error cometido es de
X/Y - Q = R/Y < 2�&.
4 .14. Divisor binario
Dados dos números X e Y naturales (X < Y), dividir X entre Y (X/Y ) consiste en calcular
dos números Q y R tales que:
� � '. � � (
� � ���… � � � ����…��
Precisión de Q : 2�& (Q tendrá p bits, todos fraccionarios)
Para calcular X/Y cuando X ≥ Y será necesario
alinear previa y convenientemente los operandos.
R < Y.2�&
13
Algoritmo de división binaria
r(0) <= x;
for i in 1 to p loop
d <= 2*r(i-1) - y;
if d < 0 then q(i) <= 0; r(i) <= 2*r(i-1);
else q(i) <= 1; r(i) <= d;
end if;
end loop;
Resultado:
Q = (q1 q2 ··· qp-1 qp)·2-p,
R = rp·2-p.
Ejemplo: X = 21, Y = 35, p = 6
Q = [100110]2 . 2-p = 38/64 = [0,100110]2,
R = 14/64 = [0,001110]2
4 .14. Divisor binario
iteración r q d comentarios
0 21 - - -
1 7 1 7 D = 42-35 = 7
2 14 0 -21 D = 14-35 = -21
3 28 0 -7 D = 28-35 = -7
4 21 1 21 D = 56-35 = 21
5 7 1 7 D = 42-35 = 7
6 14 0 <0 D = 28-35 < 0
14
4 .14. Divisor binario
Algoritmo de división binaria
r(0) <= x;
for i in 1 to p loop
d <= 2*r(i-1) - y;
if d < 0 then q(i) <= 0; r(i) <= 2*r(i-1);
else q(i) <= 1; r(i) <= d;
end if;
end loop;
15
� Hemos visto un conjunto de circuitos capaces de ejecutar las operaciones aritméticas
básicas de suma, resta, multiplicación y división.
� Hemos introducido, aunque muy brevemente, la representación de números negativos
mediante el complemento a 2.
4 .1RESUMEN
16
Short introduction to VHDLLluís TerésInstituto de Microelectrónica de Barcelona, IMB-CNM (CSIC)
Universitat Autònoma de Barcelona (UAB)
4 .2
CONTENTS
1. Main goals & Expected learning
2. Basics on VHDL lexical & syntax
3. VHDL Design Units
4. VHDL Sequential Sentences (selection)
5. VHDL Concurrent Sentences (selection)
6. VHDL usage for modelling, simulation and synthesis
7. Summary
4 .2
18
Main goals & Expected learning
Main goals
• VHDL syntax, main units and structure
• Fundamentals on sequential and concurrent statements
• Processes
• Component instances
• Signal assignments
• VHDL usage: modelling, simulation and synthesis
Expected learning
• Basic knowledge about VHDL language and its usage (based on examples already seen in this course)
• Be able to read and understand simple VHDL code
• Be able to write specific portions of VHDL code
• Understand the role of hardware languages in digital systems design
.24
19
Basics on VHDL lexical & syntax
Lexical elements: Reserved Words, Identifiers, Symbols, Literals
.2
Language Reserved Wordsabs access after alias all and architecturearray assert attribute begin block body bufferbus case component else elsif end entityexit file for function generate generic guardedif in inout is label library nandnew next nor not null of onopen or others out process procedure ...
Identifiers to provide specific names to VHDL eleme nts and objects- Based on character set {‘a’…’z’, ’A’…’Z’, ’0’…’9’, ’_’}- First character shall be alphabetical and ‘_’ at the end or two ‘__’ are forbidden- Upper/lower-case are indifferent and reserved words are forbiddenExamples: COUNT, aBc, X, f123, VHDL, VH_DL, ABC, q1, Q0
Symbols- 1 or 2 characters- operators, punctuation, comments, part of sent.
+ - * / ( ) . , : & ‘ < > = | # ; -- => ** := /= >= <= <> “
LiteralesBase Character Physical2#110_1010# ‘a’ ‘A’ ‘@’ 10 ns16#CA# String 2.2 V16#f.ff#e+2 “Tiempo” 50 pFDecimal “110101” Bit String12 0 1E6 X”F0f” B”111_100”
4
Basics on VHDL lexical & syntax
VHDL Objects
• VHDL object is any language element able to contain a value
• Types of VHDL objects:
� Constant
� Variable
� Signal
� File
.2
Object definition:<Object type> <identifier> : <data type> [:= Initial value];
constant PI : real := 3.1415927; constant WordBits : natural := 8;constant NumWords : natural := 1024;constant TotBits : natural := WordBits * NumWords;
Variables declaration
variable Counter : integer :=0;variable Increment : integer;
Increment := 2;Counter := Counter + Increment;
Variables assignment
signal Clk : bit := ‘0’;...Clk <= ‘1’;
Signal declaration& initialization
Signal assignment
file Estimuli : FileTypeName1 open read_mode is “data.in”;file Dataout : FileTypeName2 open write_mode is “data.out”;
4
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4Basics on VHDL lexical & syntax .2VHDL Data Types
• The VHDL is a strongly typed language
• A data type defines a set of fixed and static values
• Any language object belongs to a specific data type
• Object values shall belong to related data type
• New data types could be user definedtype boolean is (false, true);type bit is (‘0’, ‘1’);type severity_level is (note, warning, error, failure);type character is (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DEL, DC1, DC2, DC3, DC4, DC5, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, ‘ ‘, ‘!’, ‘”’, ‘#’, ‘$’, ‘%’, ‘&’, ‘’’, ‘(‘, ‘)’, ‘*’, ‘+’, ‘,’. ‘-’, ‘.’, ‘/’, ‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, ‘9’, ‘:’, ‘;’, ‘<‘, ‘=‘, ‘>’, ‘?’, ‘@’, ‘A’, ‘B’, ‘C’, ‘D’, ‘E’, ‘F’, ‘G’, ‘H’, ‘I’, ‘J’, ‘K’, ‘L’, ‘M’, ‘N’, ‘O’, ‘P’, ‘Q’, ‘R’, ‘S’, ‘T’, ‘U’, ‘V’,‘W’, ‘X’, ‘Y’, ‘Z’, ‘[‘, ‘\’, ‘]’, ‘^’, ‘_’, ‘`’, ‘a’, ‘b’, ‘c’,‘d’, ‘e’, ‘f’, ‘g’, ‘h’, ‘i’, ‘j’, ‘k’, ‘l’, ‘m’, ‘n’, ‘o’, ‘p’,
‘q’, ‘r’, ‘s’, ‘t’, ‘u’, ‘v’, ‘w’, ‘x’, ‘y’, ‘z’, ‘{‘, ...);type integer is range -2.147.483.647 to 2.147.483.647;type real is range -1.0e38 to 1.0e38;…/…
STANDARD package: Predefined Types of VHDL
22
4Basics on VHDL lexical & syntax .2VHDL Data Types
• The VHDL is a strongly typed language
• A data type defines a set of fixed and static values
• Any language object belongs to a specific data type
• Object values shall belong to related data type
• New data types could be user defined
type time is range 0 to 1e20units
fs;ps = 1000 fs;ns = 1000 ps;us = 1000 ns;ms = 1000 us;sec = 1000 ms;min = 60 sec;hr = 60 min;
end units time;
23
Basics on VHDL lexical & syntax .2VHDL Operators and expressions
• Operators are symbols identifying specific operations
• Types: arithmetic, logic, relational and concatenation
• Operands:
Relational
=/=<
<=>
>=
Logic
andor
nandnorxornot
Arithmetic
+-*/
**modremabsConcatenation
&
Arithmetic(-b + sqrt(b**2 - 4.0*a*c))/(2.0*a)
ConcatenationBitSign & VectorValue
Relationaldelay >= 20 nsname < “Smith”
Logic(a xor b) and not c;
• Expressions:
• Expressions could be assigned to:
� Constants (const := expression; )
� Variables (var := expression; )
� Signals (sig <= expression; )
4
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VHDL Design Units .2VHDL is organized on different “Design Units”:
• Entity
• Architecture
• Package (declaration & body)
• Configuration
EntityDeclaration
ConfigurationDeclaration
PackageDeclaration
Prim
aryS
ecundary
PackageBody
Architecture1
Architecture2
Architecturen
4
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VHDL Design Units .2ENTITY
• Like a “black-box” just describing external interface for a module while
hiding its internal architecture
• Syntax:
entity <id> is[<generics>];[<ports>];[<declarations>];
[ begin <sentences>];end [entity] [<id>];
Entity name (module name)
Generic parameters
Input/Output ports (electrical interface)
Global declarations (common to any potential architecture of this entity)
Passive sentences (common to any potential architecture of this entity)
MUX21AB
CtrlZ
entity MUX21 isport ( A : in bit;
B : in bit;Ctrl : in bit;Z : out bit;
end MUX21;
4
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VHDL Design Units .2ENTITY
• Like a “black-box” just describing external interface for a module while
hiding its internal behaviour and architecture
• Syntax:
entity <id> is[<generics>];[<ports>];[<declarations>];
[ begin <sentences>];end [entity] [<id>];
Entity name (module name)
Generic parameters
Input/Output ports (electrical interface)
Global declarations (common to any potential architecture of this entity)
Passive sentences (common to any potential architecture of this entity)
MUX21
n
BCtrl
ZA
n n
entity MUX21n isgeneric ( n : integer := 2);port ( A : in bit_vector(n-1 downto 0);
B : in bit_vector(n-1 downto 0);Ctrl : in bit;Z : out bit_vector(n-1 downto 0));
end MUX21;
Bus size as generic parameter
4
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VHDL Design Units .2ARCHITECTURE
• Details what is behind an “Entity” while describing its behaviour at functional,
data-flow, structural or mixed levels
• Multiple Architectures fo a single Entity are possible
• Syntax:
architectura <id> of <id_entity> is[<declarations>];
begin<concurrent sentences>;
end [ architecture ] [<id>];
Architecture name
Signals, variables, components …
Concurrent sentences:• Concurrent assignments• Instances to components• Processes• Blocks
Entity name
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entity MUX21 isport ( A, B, Ctrl : in bit;
Z : out bit);
end MUX21;
VHDL Design Units: Entity & Architectures .2
architecture Functional of MUX21 isbegin
process (A, B, Ctrl)begin
if Ctrl = ‘0’ thenZ <= A;
elseZ <= B;
end if;end process;
end Functional;
MUX21AB
Ctrl Z
entity MUX21n isgeneric ( n: natural);port ( A : in bit_vector(n-1 downto 0);
B : in bit_vector(n-1 downto 0);Ctrl : in bit;Z : out bit_vector(n-1 downto 0));
end MUX21;
architecture Functional of MUX21n isbegin
process (A, B, Ctrl)begin
if Ctrl = ‘0’ thenZ <= A;
elseZ <= B;
end if;end process;
end Functional; MUX21nAB
CtrlZ
n
n n
4
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VHDL Design Units : Entity & Architectures .2
architecture DataFlow of MUX21 issignal Ctrl_n, N1, N2 : bit;
beginCtrl_n <= not Ctrl;N1 <= Ctrl_n and a;N2 <= Ctrl and b;Z <= (N1 or N2);
end DataFlow;
entity MUX21 isport ( A : in bit;
B : in bit;Ctrl : in bit;Z : out bit;
end MUX21;
architecture structural of MUX21 issignal Ctrl_n, N1, N2 : bit;component INV
port ( Y : in bit;Z : out bit);
end component;component AND2
port ( X, Y : in bit;Z : out bit);
end component;component OR2
port ( X, Y : in bit;Z : out bit);
end component;begin
U0: INV port map (Ctrl, Ctr_n);U1: AND2 port map (Ctrl_n, A, N1);U2: AND2 port map (Ctrl, B, N2);U3: OR2 port map (N1, N2, Z);
end structural;Concurrent Statements
4
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VHDL Design Units .2PACKAGE
• Useful for code reuse as it could contain definitions of data types, functions and
language objects (constants, variables, signals or files) for its use on different codes
• Two units:
� “Package declaration”
� “Package body”
• Package usage
package <identifier>[<declarations>];
end [ package ] [<identifier>]
Package name
Declarations of:• Data types• Constants• Functions & procedures
package body <identifier>[<Assignments and
Detailed definitions>];end [ package body ] [<identifier>]
Package name
Assignments & definitions of:• Constants• Functions & procedures
use <library>.<package name>.[<identifier> | all ];
Usual packages:- STANDARD & TEXTIO- Std_logic_1164- Std_logic_arith
4
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VHDL Design Units .2PACKAGE
package VSuP_Pack is
-- Processor basic dimensionsconstant ProcWordBits : integer; -- Processor word lenght (bits)constant MemAdrBits : integer; -- Memory address lenght (bits)constant CtrlBusNumBits : integer; -- Number of bits for control busconstant StatusBusNumBits : integer; -- Number of bits for status and flags busconstant ALUopNumBits : integer; -- Number of bits to especify the ALU operation codeconstant OpCodeNumBits : integer; -- Number of bits to especify the instruction OpCodeconstant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 0’sconstant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 1’sconstant One : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant value ‘1’;
-- Mnemonics for ALU operationsconstant NoOp,Add,Sub,IncL,IncR,DecL,DecR,AndL,
OrL,NotL,LSh,RRot,GoL,GoR,Out0,Out1 : std_ulogic_vector (ALUopNumBits-1 downto 0);
-- Processor instruction set OpCodesconstant LDA, STA,MOV,SAV,CLR,SET,LAND,LNOT,LOR,SHIL,ROTR,
ADD,SUB,INC,DEC,CMP,BRZ,BRN,JMP,NOP,EOP : std_ulogic_vector (OpCodeNumBits-1 downto 0);
end package VSuP_Pack;
VHDL constant object Constant Id.Constantdata type Comment
4
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VHDL Design Units .2PACKAGEpackage body VSuP_Pack is
-- Processor basic dimensionsconstant ProcWordBits : integer := 16; -- Processor word lenght (bits)constant MemAdrBits : integer := 16; -- Memory address lenght (bits)constant CtrlBusNumBits : integer := 25; -- Number of bits for control busconstant StatusBusNumBits : integer := 5; -- Number of bits for status and flags busconstant ALUopNumBits : integer := 4; -- Number of bits to especify the ALU operation codeconstant OpCodeNumBits : integer := 5; -- Number of bits to especify the instruction OpCodeconstant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>‘0’);constant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>‘1’);constant One : std_ulogic_vector (ProcWordBits-1 downto 0) := conv_std_logic_vector (1,
ProcWordBits); -- Mnemonics for ALU operations
-- No operation cycleconstant NoOp : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0000";-- Addition: Out <- A + B;[C,N,Z]constant Add : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0001";-- Subtraction: Out <- A - B;[C,N,Z]constant Sub : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0010";
… / …-- Put all output bits at '1': Out <- "1...1";[N]
constant Out1 : std_ulogic_vector (ALUopNumBits-1 downto 0) := "1111";
end package body VSuP_Pack;
Constant values definition.4
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VHDL Summary (part-I) .2Session summary
• Basics on VHDL lexical and syntax
� Language lexical elements
� Objects (constant, variable, signal and files)
� Data types, Operators and expressions
• VHDL design units
� Entity and Architecture
� Configuration
� Package (declaration & body)
• Simplified formal VHDL design units descriptions but example based learning
4
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Short introduction to VHDL (cont.)
Lluís TerésInstituto de Microelectrónica de Barcelona, IMB-CNM (CSIC)
Universitat Autònoma de Barcelona (UAB)
4 .3
VHDL Sentences (selected subset) .3Sequential vs. Concurrent Sentences
• Sequential
� Algorithmic sentences like for SW languages (if, case, loop, exit, return, …)� Interpreted sequentially � Order of sentences is important for the results
� Only used in functions, procedures and Processes
• Concurrent
� Devoted to express hardware structure (Hw components and blocks are doing concurrently)
and processes working simultaneously
� Some sequential sentences have its equivalent concurrent ones
� Selected sentences: Process, Signal assignments, Components instantiation
� Mainly used in Architectures
• Concurrent to Sequential for simulation
� Each concurrent statement could be translated to its equivalent Process based on sequential
statements.
� For simulation purposes all the concurrent statements are translated to related processes.
� VHDL event driven simulation will manage just a lot of processes.
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VHDL Sentences (small selection) .3Sequential Sentences
• Where are possible?
• Which are the selected sentences?
• Variable & Signal assignments
• Wait
• If … then … else … endif
• Case
• Loop, Exit and Next
• Functions & Procedures
• Assert…report…severity
processbegin-- sequential-- sentencesend process;
function F() returnbegin-- sequential-- sentencesend F;
procedure P() isbegin-- sequential-- sentencesend P;
4
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VHDL Sentences (small selection) .3Sequential Sentences: Variable Assignment
• Immediate replacement of variable value.
• Syntax:
• Examples:
[label:] <variable name> := <expression>;
Var := ‘0’;Vector := “00011100”;string := “Message is: ”;A := B;B := my_function(3,databus)C := my_function(4,adrbus) + A;
4
38
VHDL Sentences (small selection) .3Sequential Sentences: Signal Assignment
• Projects a new event (value, time) on the signal driver.
• Syntax:
• Next sentence sequences will exchange the values
between signal “A” and “B”:
• Delay types: “inertial” or “ transport”
• Examples:
[label:] <signal_name> <= [delay_type] <expression> { after <delay>};
A <= B;B <= A;
B <= A;A <= B;=
B1 <= transport A after 10 ns;B2 <= A after 10 ns;B3 <= reject 5 ns A after 10 ns;
A <= ‘0’, ‘1’ after 10 ns, ‘0’ after 15 ns, ‘1’ after 20 ns,‘0’ after 28 ns, ‘1’ after 40 ns, ‘0’ after 50 ns;
0 10 3020 40 50 60 70(ns)
A
B1
B2
B3
A
driver
t 0 10 15 20 28 40 50
v 0 1 0 1 0 1 0
t t0 t1 … ti
v v0 v1 … vi
4
VHDL Sentences (small selection) .3Sequential Sentences: Wait
• Indicates the point where a process execution shall be suspended, as well as the
conditions for its reactivation. More than one “wait” sentence per process is possible.
• Syntax:
• Basic examples:
[label:] wait [ on <signal> {, ...}][ until <boolean_expresion>][ for <time_expresion>];
processbegin
<sequential sentences>wait ;
end process ;
Without reactivation condition
a, b;
processbegin
c <= a and b;wait on a, b;
end process ;
Sensible to events on signals “a” “b”
processbegin
Clock <= not Clock; wait for 10 ns ;
end process ;
Suspends and fixes a time for reactivation 10ns
processbegin
q <= d;wait until Clock = ‘1’;
end process ;
Sensible to events on signals & condition=True
4
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VHDL Sentences (small selection) .3Sequential Sentences: If … then … else … endif;
• Selects the group of sentences to execute depending on a Boolean condition.
• Syntax:
• Examples:
[label:] if <condicion> then<sentencias secuenciales>
{elsif <condicion> then<sentencias secuenciales}
[else<sentencias secuenciales>]
end if [label];
Latch: process beginif load =‘1’ then
Q <= D;end if;wait on load, D;
end process;
Latch
processbegin
if Enable =‘1’ thenSalida <= Entrada;
elseSalida <= ‘Z’;
end if;wait on Enable, Entrada;
end process;
Buffer Triestate
Process (A, B, Ctrl)Begin
if Ctrl = ‘0’ thenQ <= A;
elseQ <= B;
end if;end process;
Mux
[label:] if <condicion> then<sentencias secuenciales>
{ elsif <condicion> then<sentencias secuenciales}
[ else<sentencias secuenciales>]
end if [label] ;
4
41
VHDL Sentences (small selection) .3Sequential Sentences: Case
• Selects the group of sentences to execute
depending on a expression value.
• Syntax:
� Or of values: when “00” | “01”
� Values range: when 5 to 12 (integers)
� Last option: when others
• Examples:
[label:] case <condition> is{ when <value> =><sequential sentences>;}[ when others =><sequential sentences>;]
end case [label] ;
processbegin
case Day iswhen Monday to Friday =>
Daytype <= Workingday;when Saturday | Saunday =>
Daytype <= Holiday;end case;wait on Day;
end process;
type weekdays : (Monday, Tuesday, Wednesday, Thursday, Friday, Saturday, Sunday);type typeofday : (Workingday, Holiday);Signal Day : Weekdays;Signal Daytype : typeofday; process
begincase ValEnt is
when 0 => Res := 5;when 1 | 2 | 8 => Res := ValEnt;when 3 to 7 => Res := ValEnt + 5;when others => Res := 0;
end case;wait on ValEnt;
end process;
4
42
4VHDL Sentences (small selection) .3Sequential Sentences: If & Case
• Previous example with two “Process”:
� Mux
� Latch
entity LatMux isport(
Load : in bit;A, B, C, D : in bit;Ctrl : in bit_vector(0 to 1);Y : out bit);
end LatMux;
architecture TwoProc of LatMux isSignal X : bit;begin
Mux: process (Ctrl, A, B, C, D);begin
case Ctrl iswhen “00” => X <= A;when “01” => X <= B;when “10” => X <= C;when “11” => X <= D;
end case;end process;
Latch: process (Load, X);begin
if Load=‘0’ thenY <= X;
end if;end process;
end TwoProc;
A
B
Ctrl
YC
D
Load
LatMux
X
Sequential Statements
Concurrent Statements
43
VHDL Sentences (small selection) .3Sequential Sentences: Loop
• Sequential sentences in the loop region are repeated for a number of times.
• Types of loops: “while”, “for” and “without iterations control (infinite loop)”.
• Syntax:
• Examples: “Full-adder”
[label:] [ while <boolean_condition> | for <repetition_control>] loop
<sequential sentences>}end loop [label] ;
entity ParallelAdder isgeneric (n : natural :=4 );port ( X, Y : in
std_logic_vector(n-1 downto 0);Cin : in std_logic;Z : out std_logic_vector(n-1 downto 0);Cout : out std_logic);
End ParallelAdder ;
achitecture Functional of ParallelAdder isbegin
process (X, Y, Cin);variable C : std_logic_vector(n downto 0);variable tmp : std_logic;variable I : integer ;begin
C(0) := Cin;for I in 0 to n-1 loop
tmp := X(I) xor Y(I);Z(I) <= tmp xor C(I);C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop ;Cout <= C(n);
end process ;end Functional;
4
44
VHDL Sentences (small selection) .3
Sequential Sentences: Exit (inside a loop)
• Ends the loop execution when “boolean_condition” is “true” and goes to next sentence
after the loop.
• Syntax: [label:] exit [loop_label] [ when <boolean_condition>] ;
Sequential Sentences: Next (inside a loop)
• Stops current loop iteration when “boolean_condition” is “true” and goes for the next iteration
(skips current iteration after this sentence).
• Syntax:[label:] next [loop_label] [ when <boolean_condition>] ;
Needed for neested loops to identify which is the
loop to be “exited” or “nexted”
4
45
VHDL Sentences (small selection) .3Sequential Sentences: Functions (same as software languages)
• A piece of code devoted to specific computation of input parameters to return a value.
• Syntax for function declaration:
• Syntax for function definition:
• Example:
function <name> [(<parameters list>)] return <data_type>;
function <name> [(<parameters list>)] return <data_type> is{<declarative part>}
begin{<sequential sentences>}
end [function] [<name>];
Var := base + bv2int(adrBus(15 downto 8));
Sig <= base + bv2int(adrBus(7 downto 0));
function bv2int (bs: bit_vector(7 downto 0)) return integer;
Function usage
or reference
[label:] return [expresion];
4
46
VHDL Sentences (small selection) .3Sequential Sentences: Procedures (same as software languages)
• A piece of code devoted to specific computation of input parameters to return a value.
• Syntax for procedure declaration:
• Syntax for procedure definition:
• Example:
procedure <name> [(<parameters list>)];
procedure <name> [(<parameters list>)] is{<declarative part>}
begin{<sequential sentences>}
end [function] [<name>];
bv2int(adrBus(15 downto 8); Var); Var := base + Var;
procedure bv2int (bs: bit_vector(7 downto 0); x: out integer );
Procedure usage
or reference
4
47
VHDL Sentences (small selection) .3Sequential Sentences: Assert
• A kind of validation sentence: when <boolean expression> is FALSE the <string of characters>
is printed out and actions related to specified severity level are done.
• Syntax:
• Examples:
Sequential Sentences: Report
• Syntax:
• Example:
[label:] assert <boolean expression>[ report <string of characters>][ severity (note | warning | error |failure);
assert not(addr < X"00001000" or addr > X"0000FFFF“) report “Address in range" severity note;
assert (J /= C) report "J = C" severity note;
[label:] [ report < string of characters >][ severity (note | warning | error |failure);
report “Check point 13”; assert FALSE “Check point 13” severity note;=
4
VHDL Summary (part-II) .3Session summary
• Sequential vs. Concurrent worlds in VHDL
• VHDL sequential sentences (inside a process, function or procedure)
� Selected sentences:
� Examples based VHDL learning
• Variable & signal assignments
• Wait
• If … then … else … endif
• Case
• Loop, Exit and Next
• Assert, Functions & Procedures
4
49
50
Short introduction to VHDL (cont.)
Lluís TerésInstituto de Microelectrónica de Barcelona, IMB-CNM (CSIC)
Universitat Autònoma de Barcelona (UAB)
4 .4
Previous comment .4
architecture Y of X is…begin
…
end Y;
entity X isbegin…end X;
4
…S<=A when Sel=‘0’ else B;Clock <= not clock after 20 ns;…
P1: process (clock, S);begin…
end process;
P2: process …
only concurrent sentences only sequential sentences
General structure of a VHDL model
52
CONTENTS
1. Main goals & Expected learning
2. Basics on VHDL lexical & syntax
3. VHDL Design Units
4. VHDL Sequential Sentences (selection)
5. VHDL Concurrent Sentences (selection)
6. VHDL usage for modelling, simulation and synthesis
7. Summary
.44
53
VHDL Sentences (small selection) .4Concurrent Sentences
• All the concurrent sentences are being evaluated simultaneously
• Where are possible?
• Entity (passive sentences)
• Block (collects concurrent sentences)
• Architecture
• Which are the selected sentences?
• Process
• Signal assignments
• Direct Assignment
• Conditional Assignment
• Selected Assignment
• Components
• Generate
• Each concurrent sentence will be translated to its equivalent process before its simulation
Concurrent sentences
architecture Y of X isbegin
end Y;
B : blockbegin
end block ;
entity X isbegin
end X;
4
54
VHDL Sentences (small selection) .4Concurrent Sentences: Process
• Contains sequential sentences to define its own behaviour
• Communicates with other processes and concurrent sentences by means of signals
• The process is an infinite execution loop able to contain “stop/wait” conditions (at least ONE!!)
• Each process is sensible to events on specific signals or conditions to launch again its execution
• Syntax:
[<label>:] process [(<signal> ,{<signal>, ...})] [ is ]<local declarations>
begin<sequential sentences>
end process [<label>];
process begin
<sequential sentences>wait on <sensitivity signals list>;
end process ;
process (<sensitivity signals list>)begin
<sequential sentences>end process ;
=
4
55
VHDL Sentences (small selection) .4Concurrent Sentences: Signal Assignment
• Syntax:
• Examples:
[label:] <signal> <= [delay_type] <expresion | waveform> {after <delay_time>};
Tmp <= A xor B after 10 ns;Z <= Tmp xor Cin after 10 ns;Cout <= (A and B) or (Tmp and Cin) after 15 ns;
W <= ‘0’, ‘1’ after 10 ns, ‘0’ after 15 ns, ‘1’ after 20 ns,‘0’ after 28 ns, ‘1’ after 40 ns, ‘0’ after 50 ns;
Cout Full Adder
A B
Cin
Z
0 10 3020 40 50 60 70(ns)
W
Waveform W
driver
t 0 10 15 20 28 40 50
v 0 1 0 1 0 1 0
4
56
VHDL Sentences (small selection) .4Concurrent Sentences: Conditional Signal Assignment
• Syntax:
• Example
[<label>:] <signal> <= [delay_type] {<expression|waveform> when <boolean expression> else }< expression|waveform> [ when <boolean expression>];
S <= A when Sel = ‘0’ else B;
process (Sel, A, B)begin
if Sel = ‘0’ thenS <= A;
elseS <= B;
end if ;end process ;
=EquivalentProcess
S <= E1 when Sel2 = “00” elseE2 when Sel2 = “11” elseunnafected when others ;
process (Sel2, E1, E2)begin
if Sel2 = “00” thenS <= E1;
elsif Sel2 = “11” thenS <= E2;
elsenull ;
end if ;end process ;=
EquivalentProcess
4
57
VHDL Sentences (small selection) .4Concurrent Sentences: Selected Signal Assignment
• Syntax:
• Example
process (Op1, Op2, Operation)begin
case Operation iswhen add => Result <= Op1 + Op2;when subs => Result <= Op1 - Op2;when andL => Result <= Op1 and Op2;when orL => Result <= Op1 or Op2;
end case ;end process ;
with Operation selectResult <= Op1 + Op2 when add,
Op1 - Op2 when subs,Op1 and Op2 when andL,Op1 or Or2 when orL;
[<label>] with <expression> select <signal> <= [delay_type]
{<expression|waveform> when <value>,}<expression|waveform> when <value>;
=
EquivalentProcess
Type opcode is (add, subs, andL, orL);Signal operation : opcode;
4
58
VHDL Sentences (small selection) .4Concurrent Sentences: Components
• Structural and hierarchical descriptions by using components defined somewhere else.
• Syntax for component declaration:
• Syntax for component reference or instantiation:
• Examples:
component <idname> [ is ][ generic (<generic parameters list>);][ port (<ports list>);]
end [ component ] [<idname>];
<label>: <idname>[ generic map (<parameters association list>);][ port map (<ports association list>);]
U2 : example port map (X, Y, W, Z)
U4 : example port map(d=>Z, a=>X, b=>Y, c=>W);
component example isport(a , b, c : in bit ;
d : out bit );end component example;
Association lists by:
• position
• name
4
59
VHDL Sentences (small selection) .4Concurrent Sentences: Components
entity FullAdder isbegin
port( X, Y, CIn : in bit ;Cout, Sum : out bit );
end FullAdder;
architecture structural of FullAdder iscomponent HalfAdder
port( I1, I2 : in std_logic;COut, Sum : out std_logic);
end component ;component OrG
port( I1, I2 : in std_logic;O : out std_logic);
end component ;signal A, B, C : std_logic;
beginU1: HalfAdder port map (X, Y, A, B);U2: HalfAdder port map (B, CIn, C, Sum);U3: OrG port map (O => COut, I1 => A, I2 => C);
end structural ;
Half Adder Half
Adder
XY
CIn Sum
COut
A
B C
U1
U2
U3
OrG
Positional association list
Nominal association list
I1 I2 Sum Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Sum <= I1 xor I2; Cout <= I1 and I2;
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60
VHDL Sentences (small selection) .4Concurrent Sentences: Generate
• Generally used to create “arrays” of component instances, but it could include any other
concurrent sentence.
• Syntax:
• Example:
<label>: {[ for <range specification> | if <condition> ]}generate
{<concurrent sentences>}end generate ;
Clk
E(N-1) E(N-2) E(0)
S(N-1) S(N-2) S(0)
DFF DFF DFF
entity Register isgeneric (N: positive);port ( Clk : in std_logic;
E : in std_logic_vector(N-1 downto 0);S out std_logic_vector(N-1 downto 0));
end Register;architecture structural of Register is
component DFFport (Clk : in std_logic;
E : in std_logic;S : out std_logic);
end component ;variable I : integer;
beginGenReg: for I in N-1 downto 0 generate
Reg: DFF port map (Clk, E(I), S(I));end generate ;
end structural;
Parallel in/out
N-bits Register
4
61
VHDL Sentences (small selection) .4
Concurrent Sentences: Assert, Procedure call and Function call
• Same usage and behaviour as the equivalent sequential ones, but in the concurrent world.
• Concurrent “Procedure call” is just like a process with procedure parameters in the sensitivity
list.
• “Function call” could be embedded in any expression inside a concurrent statement.
[label:] <Procedure name> [(<parameters>)];
Check_Timing(min_time, max_time, clk, sig_to_test, testOK);
function Check_Timing(min_time, max_time, clk, sig_to_test) returns boolean ;
assert Check_Timing(min_time, max_time, clk, sig_to_test) report “Timing error”severity ( warning );
[label:] assert <boolean expression>[ report <string of characters>][ severity (note | warning | error |failure);
4
62
VHDL Modelling, Simulation & Synthesis .44entity Exercise is end ;architecture Code of Exercise issignal a, b : std_logic_vector(3 downto 0);signal opcode : (add, sub);signal z : std_logic_vector(3 downto 0);Begin
FuT: process (a, b, opcode);variable x, y : std_logic_vector(3 downto 0);variable s : std_logic; signal sign : std_logic;begin
if a >= b then x := a; y := b; s := ‘0’;else x := b; y := a; s := ‘1’;
case opcode iswhen add then z <= x + y; sign <= ‘0’;when sub then z <= x – y; sign <= s;
end caseend process FuT;TV: process;begin
a <= “0110”; b <= “0011”; opcode <= add; wait for 100 ns;opcode <= sub; wait for 100 ns;b <= “1001”; wait for 100 ns;opcode <= add; wait ;
end process VdT;end Functional;
Function under test
Test vectors wavefroms
63
VHDL Modelling, Simulation & Synthesis .44entity Exercise is end ;architecture Code of Exercise issignal a, b : std_logic_vector(3 downto 0);signal opcode : (add, sub);signal z : std_logic_vector(3 downto 0);Begin
FuT: process (a, b, opcode);variable x, y : std_logic_vector(3 downto 0);variable s : std_logic; signal sign : std_logic;begin
if a >= b then x := a; y := b; s := ‘0’;else x := b; y := a; s := ‘1’;
case opcode iswhen add then z <= x + y; sign <= ‘0’;when sub then z <= x – y; sign <= s;
end caseend process FuT;TV: process;begin
a <= “0110”; b <= “0101”; opcode <= add; wait for 100 ns;opcode <= sub; wait for 100 ns;b <= “1001”; wait for 100 ns;opcode <= add; wait ;
end process VdT;end Functional;
Function under test
Test vectors wavefroms
64
VHDL Modelling, Simulation & Synthesis .44entity ParallelAdder is
generic (n : natural := 4);port ( X, Y : in std_logic_vector(n-1 downto 0);
Cin : in std_logic;Z : out std_logic_vector(n-1 downto 0);
Cout : out std_logic);End ParallelAdder ;
achitecture Functional of ParallelAdder isBegin
process (X, Y, Cin);variable C : std_logic_vector(n downto 0);variable tmp : std_logic;variable I : integer ;begin
C(0) := Cin;for I in 0 to n-1 loop
tmp := X(I) xor Y(I);Z(I) <= tmp xor C(I);C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop ;Cout <= C(n);
end process ;end Functional; 65
VHDL Modelling, Simulation & Synthesis .44entity ParallelAdder is
generic (n : natural := 4);port ( X, Y : in std_logic_vector(n-1 downto 0);
Cin : in std_logic;Z : out std_logic_vector(n-1 downto 0);
Cout : out std_logic);End ParallelAdder ;
achitecture Functional of ParallelAdder isBegin
process (X, Y, Cin);variable C : std_logic_vector(n downto 0);variable tmp : std_logic;variable I : integer ;begin
C(0) := Cin;for I in 0 to n-1 loop
tmp := X(I) xor Y(I);Z(I) <= tmp xor C(I);C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop ;Cout <= C(n);
end process ;end Functional;
Logic Simulation
Logic Synthesis
X
Y
Cin
Cout
Z
VHDL Summary (part-III) 4 .4Session summary
• VHDL concurrent sentences (inside an architecture, block or entity)
� Selected sentences:
• VHDL modelling, simulation & synthesis: basic concepts and flows
• VHDL Examples based learning
This ends our short introduction to VHDL language for its usage in the current…
“Digital Systems Course”
• Process
• signal assignments (uncond & cond.)
• Components
• Generate
• Assert
• Functions & Procedures
67
68
4Basics on VHDL lexical & syntax .2VHDL Data Types
• The VHDL is a strongly typed language
• A data type defines a set of fixed and static values
• Any language object belongs to a specific data type
• Object values shall belong to related data type
• New data types could be user definedtype Result is real;type mark is range 10.0 downto 0.0;...type Price is integer;type Month is range 1 to 12;...type Cardinal is (North, South, East, West);type CardKeys is (‘N’, ‘S’, ‘E’, ‘W’);type Mixed is (‘N’, South, East, ‘W’);...variable Direction : Cardinal := West;variable Var : Mixed;Signal Key : CardKeys := ‘N’;...Var := ‘N’; -- Var & Key cannot be assigned to each other asKey <= ‘E’; -- they doesn’t belongs to the same data type
69
VHDL Design Units .2CONFIGURATION
• For each component in a specific architecture selects the module (entity +
architecture to be mapped on it
• Example:
architecture structural of MUX21 issignal Ctrl_n, N1, N2 : bit;component INV
port ( Y : in bit;Z : out bit);
end component;component AND2
port ( X, Y : in bit;Z : out bit);
end component;component OR2
port ( X, Y : in bit;Z : out bit);
end component;begin
U0: INV port map (Ctrl, Ctr_n);U1: AND2 port map (Ctrl_n, A, N1);U2: AND2 port map (Ctrl, B, N2);U3: OR2 port map (N1, N2, Z);
end structural;
configuration mux21_cfg of MUX21 isfor structural
for U0 : INV use entity CMOS.INV(Funct);
for all : AND2use entity TTL.AND2(Funct);
for U3 : OR2use entity CMOS.OR2(Funct);
end for ;end mux21_cfg;
CMOS
TTL
4
70
VHDL Sentences (small selection) .3Sequential Sentences: Variable Assignment
• Immediate replacement of variable value.
• Syntax:
• Non equivalent sequences:
• Examples:
[label:] <variable name> := <expression>;
A := B;B := A;
B := A;A := B;
Var := ‘0’;Vector := “00011100”;string := “Message is: ”;A := B;B := my_function(3,databus)C := my_function(4,adrbus) + A;
4
71
VHDL Sentences (small selection) .3Sequential Sentences: Wait
• Indicates the point where a process execution shall be suspended, as well as the
conditions for its reactivation. More than one “wait” sentence per process is possible.
• Syntax:
• Basic examples:
• Other possibilities
[label:] wait [ on <signal> {, ...}][ until <boolean_expresion>][ for <time_expresion>];
processbegin
<sequential sentences>wait ;
end process ;
Without reactivation condition
a, b;
processbegin
c <= a and b;wait on a, b;
end process ;
Sensible to events on signals “a” “b”
processbegin
Clock <= not Clock; wait for 10 ns ;
end process ;
Suspends and fixes a time for reactivation 10ns
processbegin
q <= d;wait until Clock = ‘1’;
end process ;
Sensible to events on signals & condition=True
wait on a,b until c=‘1’;
wait on a, b for 10 ns;
wait until a=‘1’ for 1 ns;
wait on a, b until c=‘1’ for 10 ns;
4
72
VHDL Sentences (small selection) .3Sequential Sentences: If … then … else … endif;
• Selects the group of sentences to execute depending on a Boolean condition.
• Syntax:
• Examples:
[label:] if <condicion> then<sentencias secuenciales>
{elsif <condicion> then<sentencias secuenciales}
[else<sentencias secuenciales>]
end if [label];
Latch: process beginif load =‘1’ then
Q <= D;end if;wait on load, D;
end process;
Latch
Process (rst, clk)begin
if rst =‘0’ thenQ <= ‘0’;
elsif clk’event and clk=‘1’ thenQ <= D;
end if;end process;
FF with reset
processbegin
if Enable =‘1’ thenSalida <= Entrada;
elseSalida <= ‘Z’;
end if;wait on Enable, Entrada;
end process;
Buffer Triestate
if Ctrl = ‘0’ thenQ <= A;
elseQ <= B;
end if; Mux
[label:] if <condicion> then<sentencias secuenciales>
{ elsif <condicion> then<sentencias secuenciales}
[ else<sentencias secuenciales>]
end if [label] ;
4
73
VHDL Sentences (small selection) .3Sequential Sentences: If & Case
• Another example to combine “If” & “Case”
sentences in a single “Process”.
entity LatMux isport(
Load : in bit;A, B, C, D : in bit;Ctrl : in bit_vector(0 to 1);Y : out bit);
end LatMux;
architecture OneProc of LatMux isbegin
process (Load, Ctrl, A, B, C, D);begin
if Load=‘0’ thencase Ctrl is
when “00” => Y <= A;when “01” => Y <= B;when “10” => Y <= C;when “11” => Y <= D;
end case;end if;
end process;end OneProc;
A
B
Ctrl
YC
D
Load
LatMux
4
74
VHDL Sentences (small selection) .3Sequential Sentences: Loop
• Sequential sentences in the loop region are repeated for a number of times.
• Types of loops: “while”, “for” and “without iterations control (infinite loop).
• Syntax:
• Examples: “counter mod 16”
[label:] [ while <boolean_condition> | for <repetition_control>] loop
<sequential sentences>}end loop [label] ;
processbegin
Cont <= 0;loop
wait until Clock=‘1’;Cont <= (Cont + 1) mod 16;
end loop ;end process ;
Without iterations control (infinite loop)
Processvar I : integer ;begin
Cont <= 0;for I in 0 to 15 loop
wait until Clock=‘1’;Cont <= Cont + 1;
end loop ;wait until Clock=‘1’;
end process ;
“For” controlled loop
processbegin
Cont <= 0;wait until Clock=‘1’;
while Cont < 15 loopCont <= Cont + 1;wait until Clock=‘1’
end loop ;end process ;
“While” controlled loop
4
75
VHDL Sentences (small selection) .3Sequential Sentences: Loop, Exit & Next example (counter module 16)
entity Counter16 isport (
Clock, Rst : in bit;Count : out natural);
end Counter16;
architecture functional of Counter16 isvariable C : natural;begin
processbegin
C := 0;loop
wait until ((Clock’ event and Clock = ‘1’)or Rst = ‘1’);
exit when Rst = ‘1’;C := (C + 1) mod 16;
end loop;end process ;Count <= C;
end functional;
Counter module 16 with
asynchronous resetentity Counter16 isport (
Clock, Rst : in bit;Count : out natural);
end Counter16;
architecture functional of Counter16 isvariable C : natural;variable I : integer;begin
processbegin
C := 0;for I in 0 to 15 loop
next when I=8;C := I;wait until Clock=‘1’;
end loop;end process ;
Count <= C;end functional;
Counter module 16
which avoids value 8
4
76
VHDL Sentences (small selection) .4Concurrent Sentences: Generate
• Example: entity ShiftReg isgeneric (N: positive);port ( Clk, SIn : in bit ;
SOut : out bit);end ShiftReg;architecture structural of ShiftReg is
component DFFport (Clk, E : in bit;
S : out bit);end component ;signal X : bit_vector(0 to N-2);variable I : integer;
beginGenShReg: for I in 0 to N-1 generate
G1 : if (I=0) generateCIzq: DFF port map (Clk, SIn, X(I)); end generate ;
G2 : if (I>0) and (I<N-1) generateCCen: DFF port map (Clk, X(I-1), X(I)); end generate ;
G3 : if (I=N-1) generateCDer: DFF port map (Clk, X(I-1), SOut); end generate ;
end generate ;end structural;
N-bits Shift register
Clk
SIn SOutX(0) X(N-2)
DFF DFF DFF
4
77
VHDL Sentences (small selection) .4Concurrent Sentences: Generate
• Example: entity ParallelAdder isgeneric (n : natural),port ( X, Y : in bit_vector(n-1 downto 0);
Cin : in bit;Z : out bit_vector(n-1 downto 0);Cout : out bit);
End ParallelAdder ;architecture structural of parallelAdder iscomponent FA
port ( A, B, Ci : in bit;S, Co : out bit);
end component ;signal C : bit_vector(n downto 0);variable I : integer;begin
GenShReg: for I in 0 to N-1 generateG1 : if (I=0) generate
LSB: FA port map (X(I), Y(I), Cin, Z(I), C(I+1)); end generate ;G2 : if (I>0) and (I<N-1) generate
OtherB: FA port map (X(I), Y(I), C(I), Z(I), C(I+1)); end generate ;G3 : if (I=N-1) generate
MSB: FA port map (X(I), Y(I), C(I), Z(I), Cout); end generate ;end generate ;
end structural;
N-bits Parallel-Adder
C0=Cin
Cout=Cn
X0 Y0
FA FA FA
Xn-2 Yn-2Xn-1 Yn-1
C1Cn-1
Zn-2 Zn-1 Z0
4
78
VHDL Sentences (small selection) .4Concurrent Sentences: Generate
• Example:entity ParallelAdder is
generic (n : natural),port ( X, Y : in bit_vector(n-1 downto 0);
Cin : in bit;Z : out bit_vector(n-1 downto 0);Cout : out bit);
End ParallelAdder ;
architecture structural of ParallelAdder iscomponent FA
port ( A, B, Ci : in bit;S, Co : out bit);
end component ;signal C : bit_vector(n downto 0);variable I : integer;Begin
C(0) <= Cin;GenParAdder: for I in 0 to N-1 generate
FAstage: FA port map (X(I), Y(I), C(I), Z(I), C(I+1)); end generate ;Cout <= C(n);
end structural;
N-bits Parallel-Adder
C0=CinCout=Cn
X0 Y0
FA FA FA
Xn-2 Yn-2Xn-1 Yn-1
C1Cn-1
Zn-2 Zn-1 Z0
4
79
VHDL Modelling, Simulation & Synthesis .4
VHDL ElaborationSea of processes
VHDLSimulator
LibrariesVHDL Analyser
VHDLSource code
4
VHDL Simulation .4VHDL Event Driven Simulation Cycle
0 1 3 4 5δ
dela
yTime
Update signals drivers
∆T
Which processes shall be resumed?
. . .
STOPWait till all resumed
processes are stopped
y/ny/n y/n
y/nInitializeSignalsDrivers
?P
roce
ss-1
Pro
cess
-2
Pro
cess
-n
Updating Signals & Time
Processes Execution
Signals Initialization
4
81
VHDL Summary (part-III) 4 .4Session summary
• VHDL concurrent sentences (inside an architecture, block or entity)
� Selected sentences:
• VHDL modelling, simulation & synthesis: basic concepts and flows
• VHDL event driven simulation of processes oceans
� Simulation cycle
� δ-delay versus simulation time
• VHDL Examples based learning
This ends our short introduction to VHDL language for its usage in the current…
“Digital Systems Course”
• signal assignments
• Conditioned signal assignments
• Process
• Components
• Generate
• Assert, Functions & Procedures
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