secondary side controlled flyback converter

Alexander Connaughton MEng

Secondary Side Controlled Flyback Converter

DOCTORAL THESIS

to achieve the university degree of

Doktor der technischen Wissenschaften

submitted to

Graz University of Technology

Supervisor

Prof Dr-Ing Annette MuumltzeElectric Drives and Machines Institute

Graz University of Technology Austria

External Examiner

Prof Maryam SaeedifardSchool of Electrical and Computer Engineering

Georgia Institute of Technology USA

Graz February 2018

AFFIDAVIT

I declare that I have authored this thesis independently that I have not used otherthan the declared sourcesresources and that I have explicitly indicated all materialwhich has been quoted either literally or by content from the sources used Moreoverthe electronic version of this document uploaded to TUGRAZonline is identical tothis printed version

Date Signature

For my parents Peter amp Lizand my siblings Mark amp Emma

Contents

Abstract V

Zusammenfassung (Abstract in German) VII

Acknowledgements IX

1 Overview 111 Thesis Objectives 1

12 Credit and Contributions to State of the Art 2

13 Related Publications 3

14 Structure of Thesis 4

2 Introduction 521 Flyback Converter Topology 5

211 Comparison to Other Topologies 6

212 Fundamentals of Operation 7

213 Applications 10

214 Active Synchronous Rectification 11

215 Important Flyback Design Considerations 12

22 Devices MOSFETs 14

221 Structure 14

222 Behaviour and Characteristics 15

223 Soft Switching 17

3 Classic and State-of-the-Art Control Concepts 1931 Classic Flyback Control 20

32 Primary Side Regulation 21

33 Single IC Cross-Barrier Solutions 24

34 Flyback Efficiency 25

I

Contents

4 Secondary Side Controlled Flyback Concept 2741 Chapter Outline 2742 Concept Overview 2843 Comparison to State-of-the-Art 2944 Turn-ON Requests from Secondary Side 3045 Steady State Operation 32

5 Proving the Feasibility of the Secondary Side Controlled Flyback Concept 3351 Chapter Outline 3352 Voltage Sensing 34

521 Primary Side Switch ndash Double Pulse Response 34522 Secondary Side ndash Synchronous Rectification 37523 Secondary Side ndash Output Voltage 37

53 Constant ON-Time Control 38531 High- and Low-Line Input Voltage 40532 Coupled Inductor Design 41533 Start-Up Routine and Primary Logic 42

54 65 W Demonstrator Hardware ndash SSCF1 44541 Control Boards 44542 Coupled Inductor Design 45543 Power Board 46544 Sensing ndash Passive Component Parameters 48

55 Experimental Results 49551 Steady-State COT Operation 49552 Primary Side Drain-Source Sensing Behaviour 55553 Start-Up Routine 58554 Efficiency Measurements 60555 Loss Breakdown 61556 Effect of Proposed Secondary Side Control on Efficiency 61557 Effect of Non-Optimal Coupled Inductor on Efficiency 61558 Effect of COT Control on Efficiency 65

56 Conclusion 65

6 Improving the Viability of the Secondary Side Controlled Flyback 6761 Chapter Outline 6762 Q-ZVS Improvement 68

II

Contents

621 Calculation of Negative Current Time 69622 Primary Side Drain-Source Voltage Sensing 70

63 Synchronous Rectification Improvement 7164 Variable-ON-Time Control 72

641 Proposed Concept 72642 Split Control Structure 75643 Start-Up Routine 75644 Calculating Inductances for VOT Control 76

65 65 W Demonstrator Hardware ndash SSCF2 77651 150 kHz Power Board 77652 Control and Adapter Boards 78653 Coupled Inductor Design 79654 EMI-Filter for VOT 80655 Drain-Source Voltage Sensing 81

66 SSCF2 VDS Sensing Measurements 82661 Primary Side 82662 Secondary Side 83

67 VOT Measurements 85671 Steady State Operation 85672 Load Jumps 87673 Natural Current Limiting 89

68 Efficiency Losses and Frequency Variation 91681 Measurements 91682 Switching Frequency Variation 92

69 Conclusions 94

7 Expanding the Capability of the Secondary Side Controlled Flyback 9571 Chapter Outline 9572 Soft Negative Current Turn-ON Requests 96

721 Effects of Irregular Secondary Turn-ON Voltage 96722 Hardware 97723 Frequency Variation 99724 Efficiency 100

73 VF-VOT Concept 101731 Proposed Concept 101732 Hardware and Control Set-Up 102

III

Contents

733 Measured Switching Frequency and ON-time Behaviour 103734 Efficiency 106

74 Reverse Power Flow for Multiple Output Voltages 108741 Proposed Concept 108742 Secondary Side VOT for Safe Reverse Power Flow 109743 Constraints on Minimum Negative Current Time 111744 Measurements 112

75 Conclusion 114

8 Conclusions 11581 Summary 115

811 Feasibility 116812 Viability 116813 Capability 117

82 Outlook Short Term Further Work 11883 Outlook Wide Band Gap Devices 119

831 Turn-ON Request Loss 119832 Reverse Power Flow 119

Symbols and Abbreviations 121

Bibliography 125

A List of Experimental Equipment 135

IV

Abstract

The ever increasing market for consumer electronics warrants continual industrialinterest in consumer power supplies particularly for laptop tablet and mobile phonecharging adapters Consequently universal adapters compatible with multiple de-vicesoutput voltages promise to become the new standard The Flyback topologyis a popular choice for adapters due to its low parts count and it is becoming a moreattractive option for medium power (50-100 W) adapters as component performanceimproves and as innovative Flyback control strategies are discovered

This thesis presents a novel Flyback control strategy herein referred to as theSecondary Side Controlled Flyback concept In contrast to the conventional controlapproach this concept proposes moving the controller from the input side to theoutput side and communicating back to the primary switch via the coupled inductoritself This provides direct access to the output voltage allowing simpler faster andmore precise output voltage sensing without the need for any additional optical ormagnetic coupling for cross-isolation ldquocommunicationrdquo

The aim of this thesis is to investigate the conceptrsquos feasibility viability and ca-pability To prove the feasibility novel drain-source voltage sensing circuits weredeveloped to execute the new cross-isolation ldquocommunicationrdquo approach Thesewere found to be faster than a more conventional opto-isolator approach and si-multaneously offer soft-switching To explore the conceptrsquos viability these sensingcircuits were employed on custom 65 W demonstrators upon which the perfor-mance of three control schemes was tested for load-change response switchingfrequency variation and efficiency Although low-load efficiency remains a sub-ject for future work peak full-load efficiency was measured at 9077 making theproposed concept well placed to compete with other state-of-the-art Flyback con-trol solutions This was achieved using the novel so called ldquovariable-frequencyvariable-ON-timerdquo control scheme Lastly a new reverse-power-flow concept wasdemonstrated to show the Secondary Side Controlled Flybackrsquos capability for futuremultiple-output-voltage adapter compatibility

V

Zusammenfassung

Der sich staumlndig vergroumlszligernde Markt an Konsumelektronik garantiert kontinuier-liches Interesse der Industrie an Netzteilen besonders fuumlr Laptop- Tablet- undSmartphone-Ladegeraumlte Daher ist zu erwarten dass universelle Stromversorgun-gen die kompatibel zu vielen Geraumlten und unterschiedlichen Ausgangsspannungensind zu einem neuen Standard werden Als Schaltungstopologie fuumlr solche Adapterwird wegen des geringen Bauteilaufwands haumlufig der Sperrwandler verwendetder aber meist auf kleinere Leistungen fuumlr Telefon-Ladegeraumlte beschraumlnkt ist Den-noch gewinnt diese Topologie an Attraktivitaumlt auch fuumlr Netzteile mittlerer Leistung(50-100 W) zumal Bauteile mit verbesserten Eigenschaften verfuumlgbar und innovativeRegelungsstrategien diskutiert werden Diese Arbeit stellt eine neue Regelungsstra-tegie fuumlr Sperrwandler vor die nachfolgend als Secondary Side Controlled Flyback be-zeichnet wird Im Gegensatz zu uumlblichen Regelverfahren wird die Regelung von derEingangs- zur Ausgangsseite verlagert und die Kommunikation zum Primaumlrschalteruumlber den Leistungs-Uumlbertrager selbst bewerkstelligt Der damit ermoumlglichte direk-te Zugriff auf die Ausgangsspannung durch die Regelschaltung erlaubt einfachereschnellere und genauere Messung der Ausgangsspannung ohne zusaumltzliche uumlberdie Isolationsbarriere optisch oder magnetisch uumlbertragene Kommunikation wo-durch der Bauteilaufwand weiter verringert wird Diese Arbeit untersucht die Mach-barkeit Brauchbarkeit und Eignung dieses Konzepts Zum Nachweis der Machbar-keit wurden neue Schaltungen zur Messung der Drain-Source-Spannung entwickeltum die neue Signaluumlbertragung uumlber die Isolationsschwelle hinweg umzusetzenund gleichzeitig verlustfreies Schalten anzubieten Um die Brauchbarkeit des Kon-zepts auszuloten wurden diese Messschaltungen in einem 65 W-Demonstrator ein-gesetzt womit die Leistungsfaumlhigkeit von drei Regelungsstrukturen im Hinblick aufLastspruumlnge Aumlnderung der Schaltfrequenz und Wirkungsgrad getestet wurde BeiNennlast wurde ein maximaler Wirkungsgrad von 9077 gemessen Schlieszliglichwurde ein neues verlustfreies Verfahren zur Verringerung der Ausgangsspannungmittels Leistungsumkehr demonstriert um Kompatibilitaumlt mit kuumlnftigen Netzteilenfuumlr mehrere waumlhlbare Ausgangsspannungen zu erzielen

VII

Acknowledgements

Firstly I would like to thank Annette Muumltze for her unwavering support throughoutmy time at TU Graz and Maryam Saeedifard for evaluating this thesis

Secondly there are six people without whom this thesis would not have been possi-ble With this in mind I would like to thank

Klaus for his immeasurable supply of measurement advice

Stephan for ldquobrutalgelaumlndernrdquo and the near-death experience on Koralm

Ewald for his encyclopaedic knowledge of where things are kept

Werner for the office companionship and the California road-trip

Ken for the best telephone tech-support in the multiverse

and Christiane for an entirely platonic work relationship

Thank you all

IX

Chapter 1

Overview

11 Thesis Objectives

In co-operation with Infineon Technologies Austria AG this thesis presents an inves-tigation of a novel power adapter concept the Secondary Side Controlled Flybackconverter The fundamentals of this new concept (detailed in Chapter 4) were pre-sented to the author by Infineon Technologies Austria AG in late 2013 and acted asthe starting point for the research conducted by the author The overall researchobjective can be summarised as follows

ldquoTo investigate the feasibility viability and capability of the Secondary Side ControlledFlyback converter concept as a real-world power adapter solutionrdquo

The target application for this concept was for a 65 W universal adapter for consumerelectronics providing a clean 20 VDC output from either high- or low-line inputvoltage (120 VRMS or 230 VRMS) To achieve the above objective within this contextthe author focused on four diverse yet interrelated sub-objectives

bull To design precise yet inexpensive drain-source voltage sensing circuits forreliable operation

bull To develop a control scheme with as much regulation on the secondary side aspossible while achieving good power adapter performance

bull To demonstrate competitive efficiency using the proposed sensing circuits andcontrol scheme on a working prototype

bull To explore any unique features and advantages that may arise from a controllerplaced on the secondary side of the Flyback converter

1

Chapter 1 Overview

12 Credit and Contributions to State of the Art

While all prototyping measurements and analyses presented in this thesis are thesole work of the author the credit for some important novel ideas is split betweenthe author and Infineon Technologies Austria AG Tab 11 summarizes the contributionfrom each side

Table 11 Credit for origin of specific novel ideas presented in this thesis

Infineon Technologies AG Author

Secondary Side Controlled Flyback Constant ON-time ControlVariable ON-time Control (concept) Double-pulse Primary Side Sensing

Reverse Power Flow (concept) Start-Up RoutineLossless Synchronous Rectification SensingVariable ON-time Control (Implementation)

Transformer Design Approach for COT and VOTDouble-Pulse Primary Side Sensing for Q-ZVS

Soft Negative Current Turn-ON requestsVariable Frequency Variable ON-time Control

Reverse Power Flow (Implementation)VOT Reverse Power Flow

All prototype development including simulation PCB design and experimentalanalysis was undertaken by the author

2

13 Related Publications


This thesis resulted in the following scientific publications

List of Journal Publications

ldquoInvestigation of a Soft-Switching Flyback Converter with Full Secondary SideBased Control - Alexander Connaughton Arash P Talei Kennith Leong Klaus KrischanAnnette Muetze

Published in IEEE Transactions on Industry Applications pp 1-15 NovemberDecember 2017 - Print

ISSN 0093-9994

ldquoVariable ON-time Control Scheme for the Secondary Side Controlled FlybackConverter - Alexander Connaughton Arash P Talei Kennith Leong Klaus KrischanAnnette Muetze

Submitted to IEEE Transactions on Power Electronics November 2017 - Currently Under Review

ldquoSecondary Side Controlled Flyback with Improved Efficiency and Reverse Po-wer Flow - Alexander Connaughton Kennith Leong Klaus Krischan Annette Muetze

Submitted to IEEE Transactions on Power Electronics November 2017 - Currently Under Revision

List of Conference Publications

ldquoNew Control Concept for Soft-Switching Flyback Converters with Very HighSwitching Frequency - Alexander Connaughton Kennith Leong Klaus KrischanAnnette Muetze

Presented atin IEEE Applied Power Electronics Conference and Exposition (APEC) pp 355-361

March 2016

ldquoQuasi-Constant Frequency Secondary Side Controlled Flyback Concept withVariable ON-Time - Alexander Connaughton Arash P Talei Kennith Leong GiuseppeBernacchia Gerald Deboy

Presented atin PCIM Europe 2017 International Exhibition and Conference for Power Conversion

and Intelligent Motion pp 1-8 May 2017

3

Chapter 1 Overview

14 Structure of Thesis

The main body of work for this thesis begins with an introduction to the Flybackconverter in Chapter 2 Elementary explanations for several concepts pertinent to thepresented research are included Chapter 3 gives an overview of the existing state-of-the-art for advanced Flyback converter concepts with reference to the precedingfundamentals

Chapter 4 details the original Secondary Side Controlled Flyback concept as initi-ally presented to the author and how this concept expands upon the state-of-the-art

Subsequent Chapters 5 6 and 7 present the authorrsquos research in approximatelychronological order with each chapter dedicated to one part of the initial overallobjective the feasibility viability and capability of the Secondary Side Controlled Fly-back Furthermore the three sub-objectives listed in Section 11 (the drain-sourcevoltage sensing the control scheme and efficiency) are addressed within each ofthese chapters with every chapter presenting improvements based on the conclusi-ons of the preceding chapter These chapters each present several of the authorrsquos ownimprovements to the state-of-the-art and to the original Secondary Side ControlledFlyback concept itself

Chapter 8 summarizes all of these chapters assessing the original objective withreference to the preceding experimental analysis This thesis ends with suggestedfuture work that was out of the scope or time-scale of the research presented here

4

Chapter 2

Introduction

To provide context for the novel content presented in the main Chapters 5-7 thischapter gives an overview of the Flyback topology followed by a qualitative sum-mary of power MOSFETs More specific technical background pertinent to the mainchapters is given within the chapters themselves

21 Flyback Converter Topology

Fig 21 shows a schematic of the Flyback topology in its most basic form It consistsof a two-winding coupled inductor with additive polarity (L1 and L2) an activeswitch on the input side (S1) a rectifying diode on the output side (D0) and filtercapacitors CIN and COUT [1] Functionally the Flyback behaves like a buck-boostconverter offering an output voltage (VOUT) smaller or larger than the input voltage(VIN) depending on the switching duty cycle of S1

COUT

S1

L2L1

D0

Input

Output

CIN

Figure 21 Fundamental principle schematic of the Flyback converter

5

Chapter 2 Introduction

However the split inductance offers the addition of galvanic isolation betweeninput and output sides a voltage transformation from a non-unity winding turns-ratio (N) and positive output polarity [1 2] This allows isolated DC-DC powerconversion with a small parts-count Due to the typical switching frequencies andinput voltages involved modern line adapter Flybackrsquos are generally implementedusing super-junction MOSFETs as the device for S1 [3ndash5]

211 Comparison to Other Topologies

Many other comparable topologies exist for isolated DC-DC power conversionTab 21 summarizes content from [6] and [7] comparing the advantages and dis-advantages of the Flyback to other traditional topologies in (approximate) order oftypical rated output power

Table 21 Comparison of common isolated DC-DC converter topologies

Converter Advantages Disadvantages

Flyback Very low parts count Poor transformer utilizationWide operating range Inefficient for gt 100 W

Output short-circuit protection Transistor voltage prop N

Forward Low parts count Poor transformer utilizationLow output ripple Critical transformer design


Push-Pull Fair transformer utilization High parts countApplications up to 500 W Critical switching instances

Output short-circuit protection Transistor voltage is 2middotVIN

Resonant LLC Very low switching loss ComplexityOutput short-circuit protection Cont tank energization

Isolated Good transformer utilization High parts countHalf Bridge Transistor voltage is 1middotVIN Critical switching instances

Output short-circuit protection Higher transistor current

Although each topology offers inherent galvanic isolation the Flybackrsquos low partscount makes it a popular choice for low-power consumer adapters and power sup-plies despite the comparatively poor efficiency State-of-the-art Flyback efficiencyfor small laptop adapters is discussed in Section 34

6


212 Fundamentals of Operation

Fig 22 shows the two main states for a basic Flyback converter sometimes referredto as energy storage and energy transfer states Respectively they occur when S1 is ONand when S1 subsequently turns OFF [8] For each state coloured arrows are givenin Fig 22 to indicate the current flow through each inductor labelled as iL1 and iL2as well as the current flow into and out of the filter capacitors

By repeatedly turning S1 ON and OFF the Flyback alternates between energystorage and energy transfer states in order to send power from input to output Forthe following introduction circuit components are assumed to be ideal

S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN

(a) S1 ON - energy storage

S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN

(b) S1 OFF - energy transfer

Figure 22 Sketch of Flyback current flow during S1 ON and OFF periods

While S1 is ON a linear rise in the inductor core flux (φ) proportional to the inputvoltage (VIN) and inversely proportional to the number of primary turns (N1) occursThe initial core flux (φ0) may or may not be zero depending on whether the con-verter is operating in continuous conduction mode (iL2 does not fall to zero duringenergy transfer) or discontinuous conduction mode (iL2 does fall to zero during energytransfer) The peak flux (φ) occurs at the end of S1 ON period ndash at t = tON

φ = φ0 +VIN

N1tON (21)

After tON S1 turns OFF and the energy stored in the core causes current to flowthrough the secondary winding and D0 Now the flux decreases linearly and pro-portionally to the output voltage (VOUT) and number of secondary turns (N2) untilthe end of the total switching period TS (unless it first reaches zero) [2]

7


For continuous conduction mode this can be expressed as

φ(t) = φ minusVOUT

N2(t minus tON) tON lt t lt TS (22)

φ(TS) = φ minusVOUT

N2(TS minus tON) (23)

Combining (21) with (23) gives

φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)

For steady state operation (constant load output voltage and switching frequency)the net change in core flux over one period must be zero By using (25) to remove thefirst two terms of (24) rearranging and incorporating the duty cycle D = tONTS it ispossible to derive the basic relation between VIN and VOUT for the Flyback converter

VOUT =N2

N1

D1 minusD

VIN (26)

While (26) is only valid for continuous conduction mode it shows that the outputvoltage is affected by both the turns-ratio and switch timings The research in thisthesis deals mainly with discontinuous current mode and the appropriate equationsare given in Sections 4-6 By considering the inductor currents iL1 and iL2 rather thanthe core flux φ it is possible to model the Flyback using the inductance values L1

and L2 instead of the number of winding turns Eg

iL1 = iL1(0) +VIN

L1tON (27)

Although core flux can provide an intuitive understanding of the coupled inductorthe primary and secondary inductor current is often a more useful way of discussingFlyback behaviour than core flux as it can be more easily measured and used todiscuss device loss and overall power transfer As such inductor current is usedexclusively in the main chapters of this thesis

8


Since both windings are around the same core the turns-ratio of the coupled inductorcan be used to determine iL2 from iL1 resulting from the shared core flux

iL2 =N1

N2iL1 = N iL1 (28)

Generally the turns-ratio (N) can be expressed in terms of inductances L1 and L2

N =N1

N2=

radicL1

L2(29)

Similarly once S1 turns OFF and current flows through D0 the transformer effectcauses the voltage seen by the secondary winding to be imposed on the primarywinding through the turns-ratio Ie during energy transfer

VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)

It follows that during this OFF period S1 blocks both the input voltage and outputvoltage reflected through the coupled inductor Thus the subsequent drain-sourcevoltage of S1 (VDS(S1)) is

VDS(S1) = VIN +N1

N2VOUT (212)

Likewise the reflected input voltage (plus the output voltage) is blocked by D0

during the energy storage state Understanding this reflective behaviour is vitalwhen choosing a device for S1 or designing the coupled inductor This property isincreasingly exploited by modern Flyback controllers for estimating voltages acrossthe isolation barrier [9]

With ideal components the blocking voltage predicted by (212) represents thehighest voltage S1 must block However with non-ideal components peak VDS(S1)

will be higher due to turn-OFF voltage overshoot caused by leakage inductanceand parasitic capacitances and will occur immediately after S1 turn-OFF A com-mon approach to mitigating this large overshoot in order to avoid S1 breakdown isintroduced in Section 215

9


213 Applications

Due to its simplicity the Flyback topology is often employed for low power bus-to-bus DC regulation in low voltage server or telecommunication systems It isa popular choice for multiple output converters due to the possibility of easilyadding extra output windings to the same core [1 6] with different turns-ratiosthese windings can simultaneously provide multiple output voltages from a singleinput voltage bus without a complex controlregulation loop

In addition due to its low parts-count and inherent galvanic isolation a large andgrowing market for Flyback converters is in single-phase AC-DC power adapters forconsumer electronics [10] Fig 23 shows the basic Flyback converter with a dioderectification bridge between the AC grid voltage and input capacitor ndash now referredto as the DC-link capacitor (CDC-link)

COUT

S1

L2L1

UGRID

D0

CDC-link

Figure 23 Principle schematic of the grid-connected Flyback converter

This input diode bridge rectifies the sinusoidal input to a positive DC voltage albeitwith double grid-frequency ripple [6] In low power applications with large inputcapacitance or with sufficient duty-cycle control any voltage ripple on the DC-link becomes either inconsequential or manageable and the Flyback can continue tooperate as a DC-DC converter

This thesis will focus on the single phase grid connected Flyback topology shownin Fig 23 for use in a universal-input medium-power adapter application Theadvantages listed in Tab 21 alongside the proposed control approach studied inthis thesis make this a suitable context

10


214 Active Synchronous Rectification

In low output voltage applications the voltage drop of the diode rectifier D0 inFig 23 can be the dominant loss contribution [11 12] In higher power converterscore and winding loss generally become more significant although with high outputcurrent diode rectifier loss is still very large To address this D0 can be replaced witha second active MOSFET (S2) as shown in Fig 24 Placing S2 on the ground railallows low-side gate drivers to be used

COUT

S1

S2

L2L1

UGRID

CDC-link

Figure 24 Schematic of grid-connected Flyback converter with active synchronousrectification switch S2

The switching behaviour of D0 can be replicated by turning S2 ON at the beginning ofthe energy transfer state and then OFF at the end By doing so the overall behaviourof the Flyback remains unchanged but the losses associated with the D0rsquos voltagedrop have been replaced with smaller conduction losses associated with S2rsquos ONresistance [12]

In general the drawback of active synchronous rectification is the addition of anextra control signal The gate signal for S2 needs to be correctly timed in respect toS1rsquos gate signal For continuous conduction mode a pair of inverted gate signalscan be sufficient but simultaneous turn-ON of S1 and S2 should be avoided as thiswould lead to an effective short circuit on both sides For discontinuous conductionmode accurate sensing or prediction of iL2 is required in order to turn OFF S2 onceiL2 has fallen to 0 A

The concept investigated in this thesis builds upon this concept of active synchro-nous rectification for Flyback converters using discontinuous current mode

11


215 Important Flyback Design Considerations

For clarity some additional design considerations that appear frequently in Secti-ons 4-6 are introduced here within the context of the preceding introductory Flybackdiscussion

Switching Frequency

Herein switching frequency is defined as 1TS where TS is the time between S1

turn-ON instances The switching frequency of S1 (and S2) guides the design ofthe Flyback or conversely the hardware employed limits the converter to a rangeof realistic switching frequencies Tab 22 gives some examples of how switchingfrequency relates to Flyback components [2]

Table 22 Examples of components affected by switching frequency

Component Related Parameters

Coupled Inductor Core amp winding lossMOSFETs Switching amp gate loss

Input Filter Input current harmonicsOutput Capacitor Output voltage ripple

Likewise other parameters such as peak currents and rated power are also affectedby the switching frequency which further affects the overall hardware design

Coupled Inductor

The coupled inductor is the most critical component in Flyback converter designThe inductances resulting from the number of turns core material core shape andair gap determine the possible switching frequencies for a given power transferThe turns-ratio determines the viable voltage rating of the synchronous rectificationdevice due to the reflected DC-link voltage and the leakage inductance should bekept low enough to avoid large voltage overshoots across S1 at turn-OFF [5 6 8]Furthermore it should be designed to support rated power without incurring coresaturation or excessive winding loss [2] It also contributes to a significant amountof volume of the final converter impacting the eventual power density [13]

12


Snubber

A snubber provides an alternative path for the inductively maintained primarycurrent caused by energy stored in the coupled inductorrsquos leakage inductance afterS1 turn-OFF [8] Otherwise depending on the leakage inductance and turn-OFFcurrent the leakage energy may cause a voltage overshoot across S1 exceeding itsbreakdown voltage potentially destroying S1 A common snubber network dueto its simplicity and ldquotune-abilityrdquo is the resistor-capacitor-diode (RCD) networkshown in Fig 25 [5]

S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT

Figure 25 Principle schematic of a Flyback converter with S1 RCD snubber

This RCD snubber uses CSn and RSn to ldquocapturerdquo and dissipate leakage energy onceS1rsquos drain-source voltage exceeds the DC-link voltage Zener clamp solutions can besuperior for low leakage energy and several non-dissipative snubbers also exist butare often more complex [5 14 15]

Input EMI-Filter

Generally real-world switched-mode power supplies require an input filter to pre-vent electromagnetic interference (EMI) caused by high-frequency switching fromfeeding noise back to the grid [16] This is often achieved by placing an array ofL-C filters between the grid input and the rectifying diode bridge The allowabledifferential- and common-mode noise depends on the exact market location and cor-responding legal standards but maximum high-frequency emmisision is typicallyasymp 40-60 dBmicroV [8 17] Generally the EMI-filter will not have any impact on Flybackoperation but Flyback operation will affect the requirements of the EMI-filter whichwill in turn affect the physical power density of the resulting power adapter

13


22 Devices MOSFETs

For most modern adapter Flybacks power MOSFETrsquos are used for S1 (and S2) due totheir current capability and fast switching speed Highly efficient and power-denseadapters employ superior Gallium Nitride (GaN) devices [18] although cost-benefitlimitations have so-far prevented GaN based adapters from becoming ubiquitous inconsumer applications [19] The experimental verification work in this thesis wasdone using silicon power MOSFETs and this section gives a qualitative overview oftheir main characteristics

221 Structure

Several variants of the MOSFET structure exist but the most common type in powerelectronics is the N-channel type since it is ldquonormally OFFrdquo and the higher carriermobility of the n-type results in lower ON-resistance (RDS(ON)) [20] Fig 26 shows asketch of two N-channel power MOSFET structures Highly doped n+ regions formthe source (S) and drain (D) while an isolation layer separates the gate contact (G)from the underlying p and n sections

G

D

S S

n+ n+

p p

n-

n+

(a) Standard Power MOSFET

G

D

S S

n+ n+

p p

n-

n+

p+p+

(b) Super-junction MOSFET

Figure 26 Simplified sketch of vertical N-channel power MOSFETs

14

22 Devices MOSFETs

This structure leads to an npn configuration with a reverse blocking internal bodydiode from source to drain When sufficient voltage is applied between gate andsource a conductive n-channel forms between n+ regions ndash turning the MOSFETON and allowing drain to source current flow

To maximize the n regions and reduce RDS(ON) most modern high-voltage MOS-FETs utilize the charge compensation principle to some degree balancing the dopingof the n region with enlarged p wells to maintain sufficient breakdown voltage Thishas allowed devices to surpass the theoretical limit of on-resistance for a given break-down voltage the silicon limit [2 20 21] For very high blocking voltages (gt600 V)super-junction MOSFETs use a comparatively thin n- region with the p sectionsextended further into deep columns While the super-junction design can blockhigher voltages and has low RDS(ON) the deep p-columns lead to poorer switchingbehaviour and a large highly non-linear parasitic output capacitance

222 Behaviour and Characteristics

Fig 27 shows a model of the MOSFET with the parasitic capacitances that arise fromthe structure shown in Fig 26 The MOSFET is a unipolar voltage controlled devicethat approximates a closed switch when its gate-source voltage (VGS) is higher thanits threshold value VGS(th) This requires CGS and CGD to be charged and dischargedfor every turn-ON instant

G

D

S

CGD

CGS

CDS

Figure 27 MOSFET circuit model

The VGS supplied by the device driver is typically chosen to balance the loss associ-ated with charging the gate against the lower RDS(ON) and higher saturation currentpossible with higher VGS Fig 28b shows an ideal sketch of drain-current in relationto VGS and VDS

15


For super-junction MOSFETs optimum gate voltage is usually between 8-20 V Oncethe device is ON current can flow from drain to source through a resistance set by thechip dimensions and the n-channel resulting from the applied VGS Fig 28a showsa modified sketch of the super-junction structure during the conductingON-statewith an exagerated n-channel formed by the gate-source voltage [22]

G

D

S S

n+ n+

p p

n-

n+

p+p+

(a) Simplified sketch of ON state (b) Ideal MOSFET output characteristic taken from [23]

Figure 28 Super-junction MOSFET structure during ON state (a) and ideal MOSFEToutput characteristic (b)

Fig 27 indicates that by turning ON the device any excess charge stored in CGD

and CDS (together known as the lumped COSS) will discharge This contributes to theturn-ON switching loss COSS also impacts the turn-OFF behaviour of the deviceFor super-junction MOSFETs COSS is large and highly non-linear with drain-sourcevoltage which can introduce significant turn-OFF voltage ringing at high currentsFig 29 shows an example of super-junction devicersquos parasitic capacitance versusdrain-source voltage [24]

Despite their large and non-linear COSS super-junction MOSFETs are generallythe preferred device for the main switch in Flyback based adapters due to theirhigh blocking voltage (especially useful for high-line grid input voltage) and theircomparatively low ON-state resistance compared to other device types In Flybackbased adapters 600 V rated super-junction MOSFETs are very common

16

22 Devices MOSFETs

Figure 29 Parasitic capacitances of a 600 V CoolMOS C7 (IPL60R125C7) [24]

223 Soft Switching

The charge stored in COSS at turn-ON is a large contributor to turn-ON loss Byturning ON the MOSFET when the drain-source voltage is already low such losscan be reduced This is generally referred to as ldquosoft-switchingrdquo

For a Flybackrsquos synchronous rectification switch (S2) soft-switching can be achie-ved with a small dead-time allowing the load current to conduct through the body-diode for a short time before applying VGS so that the drain-source voltage falls tothe forward body diode voltage This causes S2 turn-ON switching loss to becomenegligible For the primary side MOSFET it is common to make use of the resonancebetween the coupled inductor and parasitic MOSFET capacitances they cause thedrain-source voltages to oscillate at the end of the synchronous rectification in dis-continuous current mode It is possible to turn-ON the primary switch at the valleyof such oscillation to reduce primary turn-ON switching loss [20] This is explainedwith more detail in Chapter 3 in context with a state-of-the-art control approach

17

Chapter 3

Classic and State-of-the-Art ControlConcepts

This chapter covers a selection of existing Flyback control concepts representing thestate-of-the-art currently on the market and highlighting the pros and cons of eachapproach with respect to one another The chosen concepts are

bull ldquoClassicrdquo Control

ndash The conventional control approach alluded to in Chapter 2

bull Primary Side Regulation

ndash A control approach that does not require isolated signal coupling foroutput voltage feedback measurement

bull Single IC Cross-Barrier Solutions

ndash Complete solution whereby both controller and active switch are includedin one IC package with direct VOUT access

This chapter finishes with a discussion of the achievable efficiency of 65 W Flybackconverters using these three control concepts and silicon-based power MOSFETs

19

Chapter 3 Classic and State-of-the-Art Control Concepts

31 Classic Flyback Control

Fig 31 shows a block diagram of the classical control structure superimposed ontothe Flyback schematic In its simplest form the Flyback converter is controlledfrom the primary side operating as outlined in Section 212 hard-switching witha diode in place of S2 (see Fig 21) Any VOUT feedback must be relayed via high-voltage signal coupling (often executed with opto-isolators or magnetic coupling) tomaintain galvanic isolation between input and output sides

S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER

Figure 31 Flyback converter with block diagram of conventional control structure

The controller can then compare the actual output voltage to a reference value andmodify the switching pattern of S1 accordingly Several control loop types havebeen proven to work with the Flyback converterSome well-known types includecontinuously modulated structures such as a PI controller as well as non-continuousloops such as the ldquobang-bangrdquo hysteresis controller The advantage of such anapproach is ruggedness and simplicity

When including an active synchronous rectification switch with this set-up itrequires both synchronous rectification gate signal and output voltage sensing to betransmitted via signal coupling to maintain isolation across the coupled inductor[25ndash30] Such signal coupling can often be one of the most expensive and safety-critical electronic components in the adapter

20

32 Primary Side Regulation


As shown in Section 212 and in (211) a Flybackrsquos coupled inductor causes theoutput voltage to be reflected across the primary winding during the energy transferstate (shown in Fig 22) This occurs when S1 turns OFF and the coupled inductor isde-energizing into the output capacitor By determining the primary side inductorvoltage this phenomena can be exploited to sense the output voltage from a primaryside controller without any need for isolated signal coupling For accuracy a mea-surement should be made at the start of energy-transfer as the reflected VOUT decaysduring the off-time This was first effectively demonstrated in [31] and named asprimary side regulation primary side sensing

Two main variations of the concept exist whereby VOUT is inferred either by sub-tracting the DC-link voltage from the drain-source voltage of S1 or by adding anauxiliary winding to the main inductor core [32] Although the second approachrequires an extra winding the winding can scale the inductor voltage to avoid anyhigh-voltage sensing components and is less vulnerable to high-frequency switchingnoise [33] Fig 32 shows a sketch of both variations with additional dotted lines in-dicating the voltage measurements for each approach The auxiliary circuit is takenfrom [9]

S1

L2COUT

L1 VOUT

D0

CDC-link

Primary SideRegulation

(a) S1 drain-source voltage method

S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link


(b) Auxiliary winding method

Figure 32 Diagram of two primary side regulation variations

Figs 33 and 34 show waveforms for the auxiliary winding type shown in Fig 32bfor both CCM and DCM modes of operation where VRB is the scaled inductorvoltage measured across RB The auxiliary circuit shares a ground connection withthe primary based controller allowing a straight-forward voltage measurement

21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time

Figure 33 Knee-point and typical Flyback waveforms for CCM mode [9]

S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time

Figure 34 Knee-point and typical Flyback waveforms for DCM mode [9]

Figs 33 and 34 shows that any ringing from S1 turn-OFF is also reflected to theauxiliary winding For this reason (and to minimize affect of non-ideal secondaryside voltage drops from high current) the knee point of the inductor voltage isgenerally used to infer the output voltage The same applies when adopting thedrain-source voltage approach The nature of the knee-point is different for CCMand DCM operation For CCM the knee-point gradient is easier to sense due to thenear-instantaneous reversal of inductor voltage direction

22


In contrast for DCM VRB rings with a low frequency related to the main inductancesand thus undergoes a slow change once iL2 crosses 0 A For fast knee-point detectionDCM operation thus requires some form of zero-current-crossing sensing for iL2However this would require some isolated coupling to transmit the zero crossingsignal thus nullifying a main advantage of the primary side regulation To overcomethis issue several ldquowork-aroundsrdquo exist

One such example can be summarized as approximating the knee-point instantby waiting for the first iL1 zero crossing (sensed with a shunt resistor) after a givenblanking time post S1 turn-OFF (shown in Fig 34) VRB is then immediately sampledThe sampled voltage can then be converted to output voltage with

VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)

Where VD is the forward voltage of D and N1 N2 and N3 are the number of turns forL1 L2 and L3 respectively To account for voltage drop due to leakage inductance theterm k is included where k = 1 + L1

L2

L2+Lσ2Lm

Lm is the primary magnetizing inductanceand Lσ2 is the secondary leakage inductance For the drain-source voltage approachwithout the extra winding VOUT can be approximated with

VOUT =N2

N1(VDS(S1) minus VDC-link) minus VD (32)

For a fast controller the term iL1 is negligibly small at the zero crossing (as annotatedin Fig 34) With sufficient sampling speed such an approach can yield an accurateestimate of VOUT but requires accurate knowledge of the circuit parameters andrelatively complex logic

Overall the primary side regulation approach is an effective ldquoopto-isolator-lessrdquosolution especially for CCM For DCM more effort is needed in voltagecurrentsensing Primary switching loss can be reduced by including valley switching in thecontrol logic by tracking VDS(S1) For DCM applications an independent synchronousrectification driver such as the LT8309 can be used to reduce secondary side diodelosses however this is not compatible for CCM operation (the best operation forprimary side regulation [34]) Furthermore the controller can never sense the outputvoltage in idle mode as an energy transfer state is required in order to infer VOUT

reflected across the primary switch

23


33 Single IC Cross-Barrier Solutions

In an effort to simplify Flyback design single IC controllers are available that houseboth the controller and the primary switch S1 in a single package Together with anintelligent PCB layout this can help improve power density and reduce noise onsignal tracks between controller driver and switch Power Integrations Inc extendedthis idea with the InnoSwitchTM device family by also including the synchronousrectification sensingdriver in the package with internal high voltage isolation bet-ween primary and secondary switch circuitry [35]

Fig 35 shows a schematic of the InnoSwitch3-CP with a Flyback converter By re-versing the classic Flyback control structure (Section 31) VOUT regulation is situatedon the secondary side and the primary switch is controlled via isolated magneticcoupling within the IC package

Figure 35 Schematic of the InnoSwitch3-CP controller [35]

Advantageously direct VOUT access is now possible with the secondary side circuitryThis results in simpler more reliable VOUT measurements without the need of a thirdwinding or high-voltage sensing components Furthermore active synchronousrectification can be used for both DCM and CCM as the controller is unified on thesecondary side Valley switching is also possible by using the drain-source voltageacross S2 to infer VDS(S1) However isolated signal coupling has been re-introducedonly now from the secondary controller to the primary side switch

24

34 Flyback Efficiency


A key performance criteria of a power adapter is the overall power conversionefficiency both for high- and low-line input voltage Not only does the presenceof synchronous rectification affect losses but so does the switching pattern andinductor currents that emerge from the control scheme Fig 36 shows the measuredefficiency of three bespoke 65 W adapter Flyback demonstrators each of whichuses one of the control schemes discussed thus far a demonstrator using ldquoclassicrdquocontrol taken from [36] a primary side regulation demonstrator taken from [37] anda InnoSwitch3 single IC controller demonstrator taken from [38]

0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()

High-line InnoSwitch3Low-line InnoSwitch3

High-line ldquoClassicrdquo wo Sync RecLow-line ldquoClassicrdquo wo Sync RecHigh-line Primary Side RegulationLow-line Primary Side Regulation

Figure 36 Efficiency comparison of various 65 W Flyback demonstrators examples

Although the rated power of these demonstrators was the same their physical designvaried and the achievable efficiency of a Flyback depends greatly on the converterhardware specifications eg power density winding type and complexity availablecore material snubber dimensions and breakdown voltage of S1 As such this plotshould be treated as a reference for the range of efficiencies expected of bespoke 65 WFlyback adapters All control schemes are capable of delivering asymp90 efficiencyat medium to high load and interestingly the only demonstrator employing activesynchronous rectification achieved the highest efficiency

25

Chapter 4

Secondary Side Controlled FlybackConcept

41 Chapter Outline

This chapter introduces and explains the Secondary Side Controlled Flyback conceptproposed by Infineon Technologies Austria AG and contrasts it with the state-of-the-art concepts introduced in Chapter 3 This top-level idea was the basis and startingpoint for all research contributing to this thesis

27

Chapter 4 Secondary Side Controlled Flyback Concept

42 Concept Overview

Conventionally the Flyback converter is controlled from the primary side in eitherhard-switching mode (with a diode in place of S2) or in quasi- or full-resonant modewith an active synchronous rectification switch

S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED

CONTROLLERCONVENTIONAL

CONTROLLER

Figure 41 Comparison of conventional and proposed Flyback controllers

In this case both synchronous rectification gate signal and output voltage sensingmust be transmitted via opto-isolators or magnetic coupling to maintain galvanicisolation across the coupled inductor However such isolated coupling can be rela-tively costly and cause operational issues at high frequency Standard high-voltageopto-isolators can add a propagation delay up to 100 ns to secondary gate signalsand output voltage measurement [39ndash41] (limiting achievable switching frequencyand precision in soft-switching applications) and magnetic couplers can be vulne-rable to electromagnetic noise radiated by the Flybackrsquos coupled inductor [42 43]This concept proposes removing all such isolators and instead placing the controlleron the secondary side of the coupled inductor

However unlike a synchronous rectification driver (such as the LT8309 [34]) ithas the additional function of output voltage regulation by providing turn-ON com-mands to the primary switch (S1) via the coupled inductor using pulses of negativecurrent to discharge S1rsquos parasitic output capacitance

28

43 Comparison to State-of-the-Art


Firstly moving the main controller to the secondary side enables direct access to theoutput voltage as shown in Fig 41 Direct access is advantageous in variable outputvoltage applications such as USB-Power-Delivery (USB-PD) USB-Type-C [44ndash46]where different output voltages are required depending on the load attached Anexisting USB-PD Flyback adapter from Texas Instruments Inc shown in [47] uses ahard-switching primary-based controller with opto-isolators for the output voltagefeedback loop Secondly by eliminating the need for opto-isolators the parts-count isreduced and the corresponding propagation delay between primary and secondaryside is removed The most common opto-isolator free solution is the primary-sideregulation concept whereby a primary side based controller infers the reflectedoutput voltage using the drain-source voltage across S1 However this solutionlacks the direct access to the output voltage offered by a secondary side controller

An existing secondary side based controller from Power Integrations Inc is a de-dicated IC controller that neatly incorporates the primary MOSFET and utilises aninternal magnetic feedback link for primary-secondary communication [35] Howe-ver this solution constrains a designer to the internal primary MOSFET ndash limiting theapplication of the IC to a specific frequencypower range Furthermore the productdoes not allow full zero voltage turn-ON of the primary switch

In contrast by signalling turn-ON commands to S1 via the coupled inductor anyinternal chip communication can be removed This maintains freedom of choicefor the primary device and simultaneously enables soft primary turn-ON whilestill eliminating opto-isolators Though a potential gain in efficiency might be lostdue to the negative current requests the transformer design can be relaxed as nothird winding is needed and soft switching may support volume and loss reductionwithin the EMI-filter

Table 41 Feature comparison with state-of-the-art Flyback controllers

Synchronous No Signal Direct VOUT Soft PrimaryController Rectification Coupling Access Turn-ON

Proposed Concept X X X XInnoswitch-CP X ndash X ndash

TI TPS25740 ndash ndash X XFairchild SEZ1317 ndash X ndash X

29


Tab 41 compares features of the proposed concept against the aforementioned state-of-the-art Flyback controllers The central improvement to the state-of-the-art is thatthe primary drain-source voltage (VDS(S1)) provides the signal to turn ON the primaryswitch (S1) rather than auxiliary digital or magnetic signals The following sectionexplains in more detail how this is possible with a secondary side based controllerA market-ready incarnation of the proposed concept would be a pair of IC chipscontaining the secondary side controller and the simple primary side drain-sourcesensing with discrete logic as depicted in Fig 42

S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side

CONTROLLERPrimary Side

Slave Logic

Figure 42 Proposed secondary side controller with independent primary side logic

44 Turn-ON Requests from Secondary Side

After start-up and with the output capacitor charged it is possible to energize thesecondary inductor with ldquonegative currentrdquo (away from the load) by turning ON S2Subsequently turning OFF S2 will rapidly change the direction of secondary didtand the magnetic field will de-energize on the primary side discharging the parasiticoutput capacitance (COSS) of S1 [48] The turn-ON signal for S1 comes from a zero-voltage detection circuit connected to S1rsquos drain Thus the secondary side controllercan request energy from the primary side by ldquosendingrdquo a small negative currentpulse sufficient to discharge the parasitic output capacitance of S1 and cause a zerovoltage crossing When turning ON S1 at this instant soft-switching is achieved witha zero-voltage-switching (ZVS) turn-ONA sketch of such a ZVS turn-ON request isshown in Fig 43 in context with VDS(S1) inductor currents and gate signals

30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold

Figure 43 Sketched close up of proposed turn-ON request using negative current

INEG is a constant defined as the minimum negative sedcondary side current requiredto induce a zero crossing of VDS(S1) in this way Assuming constant COSS a minimumestimate of INEG can be found using (42) although a slightly larger INEG should beused in reality to accommodate non-linear COSS and leakage inductance [49] INEG isrelated to the energy stored in the main inductance of the coupled inductors and thestored charge in S1rsquos output capacitance (QCOSS) [50]

QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic

QCOSSVDC-link N2L1 (42)

where N is the coupled inductorrsquos turns-ratio VDC-link is the voltage across CDC-link

and L1 is the primary inductance as shown in Fig 41 INEG should be dimensioned forthe peak DC-link voltage TNEG should be sufficient to achieve this negative current

TNEG = INEGL2 VOUT (43)

31


45 Steady State Operation

A sketch showing turn-ON requests and TNEG in the context of steady-state operationcan be seen in Fig 44 Whenever the output voltage VOUT falls below a referencethreshold the secondary side can request energy from the primary side by turningON S2 for a time TNEG ndash ldquosendingrdquo a ldquoturn-ON requestrdquo using negative current Ineffect this allows the coupled inductor to transmit the turn-ON request to S1 afterwhich S1 turns ON to return more energy to push VOUT back above the referencethreshold By repeating this process steady-state Flyback operation is achievedusing the novel turn-ON requests transmitted from the secondary side

gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST

Figure 44 Secondary side controlled Flyback turn-ON requests with gate signalsVOUT inductor currents and drain-source voltages

32

Chapter 5

Proving the Feasibility of theSecondary Side Controlled FlybackConcept

51 Chapter Outline

This chapter aims to demonstrate the feasibility of the Secondary Side ControlledFlyback A 65 W demonstrator was built with two key objectives

bull Supply a stable output voltage at competitive efficiency using minimal primaryside control and a working start-up routine

bull Achieve reliable control of the primary switch via the coupled-inductor withsignal ldquopropagation delayrdquo comparable to the best market-ready opto-isolators

Section 52 describes the novel sensing hardware used to achieve this cross-isolationcommunication Section 53 describes the proposed control scheme for regulatingthe output voltage Section 54 details parameters of the demonstrator hardwarewhile Section 55 presents measurements of

bull High- and low-line steady-state operation

bull Primary side turn-ON delay

bull Autonomous zero crossing blanking

bull Start-up routine

bull Efficiency and losses

33

Chapter 5 Proving the Feasibility of the Secondary Side Controlled Flyback Concept

52 Voltage Sensing

Reliable sensing of the zero crossing of both VDS(S1) and VDS(S2) is vital to the effecti-veness and stability of the proposed Secondary Side Controlled Flyback conceptBoth of these voltages were sensed using sub-circuits based on passive componentsand inverting high speed comparators The primary side sensing also includes anovel network to provide autonomous passive filtering between turn-ON requestsand unwanted zero voltage crossings

521 Primary Side Switch ndash Double Pulse Response

Primary drain-source voltage sensing should provide the primary side logic with aturn-ON command after sensing a zero crossing of the drain source voltage Fig 51shows the schematic of the primary side VDS sensing sub-circuit Tab 55 lists specificcomponent values used on the demonstrator

minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2

Figure 51 Schematic of circuit for detecting zero voltage crossings

The network uses a capacitive divider (C1 and C2) to scale the drain-source voltageAlthough using a simple divider would work in low frequency applications thesteep dvdt across S1 caused by a turn-ON request will also aggressively dischargethe small capacitors before the zero crossing occurs leading to an early signal fromthe comparator However adding the high-voltage diode D1 zener diode D3 andDC voltage source U1 allows the comparator to indicate both a steep dvdt event andthe following zero voltage crossing as distinct and subsequent pulses

34

52 Voltage Sensing

If the dvdt across S1 is sufficient to cause a current through the capacitive dividergreater than the maximum current from the U1R2 combination (iU(max)) C2 will dis-charge and trigger the comparator before the zero crossing just as before Howeverdue to the non-linear capacitance of super-junction MOSFETs and the triangularshape of the turn-ON request the dvdt slope softens as the parasitic capacitance ofS1 discharges closer toward 0 V

This will allow C2 to begin recharging disabling comparator output until VDS(S1)

falls below the DC supply voltage and crosses 0 V at which point the comparator willbe triggered again In summary this means that a forced discharge of S1rsquos outputcapacitance from a turn-ON request will always cause a pair of quick successiverising and falling edges from the primary comparator output ndash a double pulse

By adapting the primary control accordingly the first comparator output pulse canbe acknowledged but only a second pulse occurring within a given time windowcounts as a genuine signal to turn ON S1 As an example Fig 52 shows a measuredimplementation of this approach using hardware described later in Section 54

05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)

mdash VDS(S1)mdash QPRImdash VGS

Figure 52 Measurement of primary VDS sensing sub-circuit in operation

35


If the primary logic only responds to such double pulses the primary sensing sub-circuit can autonomously distinguish intentional zero voltage crossings (caused bythe turn-ON requests delivered from the secondary side) from undesired crossingsthat may occur during drain source voltage ringing (that cause only one pulse)There are two such ringing instances in Flyback operation

1 ldquoFlyback oscillationrdquo between the main inductances and the parasitic capa-citances of both MOSFETs while both S1 and S2 are OFF after synchronousrectification

2 Ringing after primary switch turn-OFF whereby charge oscillates between theprimary parasitic capacitance the inductance and the snubber network

In the first case the comparatively low frequency oscillations during twait incur acomparatively small dvdt If the current through C1 remains below iU(max) the capa-citance C2 never fully discharges before the actual zero crossing and the comparatoris only triggered at VDS(S1) lt 0 V

Thus the double pulse never occurs and the single pulse from the primary com-parator would be ldquoblankedrdquo and S1 would remain OFF The series resistance R2 canbe used to set the sensitivity of the networkrsquos blanking capability by limiting themaximum current from U1 It should fulfil the criteria

ω0 C1 VDS(S1) ltVU1

R2lt C1

dVDS(S1)

dt(51)

where VDS(S1) is the peak primary drain-source voltage VU1 is U1 voltage dVDS(S1)dt ismaximum expected VDS(S1) slope and ω0 is the resonant frequency between L1 andCOSS(S1) at the input voltage The upper-limit ensures that C2 discharges during steepdvdt the lower limit ensures that it does not during Flyback ringing Setting iU(max)

between these limits provides room for parameter drift and hardware tolerancesIn the second case ndash after S1 turn-OFF ndash the overshoot amplitude and frequency is

dependent on the peak inductor current COSS(S1) and the snubber The frequency istypically very high and the dvdt can exceed that caused by a turn-ON request Withinsufficient snubber damping the turn-off ringing can also cause VDS(S1) to cross 0 VAs such the peak primary current and snubber parameters should be chosen suchthat a zero crossing after primary turn-OFF is impossible This will only yield onepulse from QPRI (caused by steep dvdt) ensuring that S1 stays OFF

36

52 Voltage Sensing

522 Secondary Side ndash Synchronous Rectification

The secondary side VDS sensing for synchronous rectification must provide twosignals when VDS falls to zero (for turn-ON) and when the current falls to zero (forturn-OFF) Fig 53 shows the basic comparator circuit used to achieve this Oncethe body diode of S2 is conducting the potential at the comparatorrsquos inverting inputbecomes negative until the current through L2 and S2 falls below zero at which pointthe potential flips direction indicating that synchronous rectification has ended

R3minus

+

S2

QSR

D4

D5

Figure 53 Schematic of sensing circuit for synchronous rectification

523 Secondary Side ndash Output Voltage

The controller is fed a binary signal from another circuit indicating whether theoutput voltage is above or below a reference voltage This simple resistive dividercircuit is shown in Fig 55 The reference voltage UREF should be dimensioned to beequal to the desired output voltage scaled through R4 and R5 Once the scaled outputvoltage falls below this reference the comparator output signal will be triggered

COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2

Figure 54 Schematic of output voltage sensing circuit in context with L2 and S2

37


53 Constant ON-Time Control

Fig 55 presents waveforms of the secondary side controlled Flyback during steady-state operation The controller uses an adapted form of pulse-skipping control[51] along with triangular current mode (TCM) operation to drive the output loadgenerate the negative-current-turn-ON-requests and simultaneously achieve zerovoltage switching (ZVS) [52]

gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold

Figure 55 Sketch of COT control scheme with rising DC-link voltage

As shown in Fig 55 both switches are OFF during twait and the controller waits forthe output voltage (VOUT) to fall below its desired threshold value The secondaryswitch is then turned ON for a short time TNEG to energize the inductor to negativecurrent INEG and turned OFF again to induce ZVS on the primary side and trigger aprimary side turn-ON command Independently the primary side acts as a slave tothe secondary side controller

38


It constantly waits for its turn-ON command and once it occurs will turn ON S1 fora fixed time TON the ON-time required to deliver the rated power at the minimumpoint of expected input voltage ripple (VDC-link(min)) A different fixed ON-time isused for high- and low-line input but during operation the same turn-ON-time isexecuted irrespective of input voltage ripple or load to keep the primary-side logicas reduced as possible This as indicated by the more transparent current tracein Fig 55 (which shows the inductor current from the preceding switching cycle)shows that rising DC-link voltage results in rising peak inductor current Once TON

has elapsed the primary switch turns OFF and begins to wait again for VDS(S1) to fallbelow zero At this point S2 acts as a synchronous rectifier turning ON at VDS(S2)

lt 0 V and remaining ON while the secondary inductor de-energizes into the outputcapacitorload [12]

gggggggggggVDS(S2)lt 0 V

N

Y

S2 ON

gggggggggggiL2 lt 0 A N

Y

gggggggggggVOUTgt Vrated

Y

N

gggggggggggWait for TNEG

S2 OFF

gggggggggggVOUTlt Vrated

N

Y

S2 ONS2 OFF

Pulse-skipping

SynchronousRectification

Turn-ON Request

Figure 56 Flow chart of steady-state from perspective of secondary side controller

39


Once the secondary inductor current falls to zero the controller checks the statusof the output voltage (via a simple comparator network) and either turns-OFF S2

to begin twait and wait for the output voltage status to change (ldquopulse-skippingrdquo)or leaves S2 ON to immediately generate negative current for the next turn-ONrequest (TNEG) Fig 56 shows the basic function of the secondary side controllerWhenever the desired output voltage has been reached the secondary side refrainsfrom sending a negative current A key aspect of pulse-skipping TCM is that duringsteady-state the primary side ldquocontrolrdquo is in fact just the simple set response of afixed ON-time Due to the constant primary ON-time the converter will operatewith switching frequency that moves with the input voltage ripple and output loadWhen designing the converter a maximum desired switching frequency (f S(max))should be selected This switching frequency will occur at full load minimum pointof the input voltage ripple The ON-time needed to deliver the required power atthe minimum point of expected input voltage ripple (VDC-link(min)) can be calculatedusing the following derived formula

TON =

radic2L1PIN

VDC-link(min)2 f S(max)

(52)

The parameters VDC-link(min) PIN and L1 are defined in Section 532 Detailed analysisof primary-side based COT control for Flyback converters including control stabilityand dynamic response can be found in [53ndash55]

531 High- and Low-Line Input Voltage

From (43) and (52) it is evident that the control timings will change dependingon whether the circuit is operating from high-line (230VRMS) or low-line (120VRMS)input voltage For low-line TNEG can be shorter due to the reduced energy storedin COSS(S1) but TON should be longer due to smaller VIN across L1 Therefore bothprimary and secondary side controls should be aware of the input line voltage Theprimary side has direct access to the input voltage and the secondary side can inferVIN line voltage by sensing the reflected blocking voltage across S2 while the primaryswitch is ON during the energy storage phase (during TON)

It should be noted however that the exact DC-link voltage (varying with DC-linkripple) is irrelevant due to the constant-ON time control approach Awareness ofhigh- or low-line input voltage is sufficient

40


532 Coupled Inductor Design

With a constant-on-timevariable frequency control it is critical to dimension thecoupled inductor to supply rated power (Prated) at the lowest expected input voltage(VDC-link(min)) Ie the minimum point of the input ripple for low line input

VDC-link(min)2 = 2VRMS

2minus

Prated

CDC-link f grid(53)

Whereby VRMS is the RMS grid voltage f grid is the grid frequency in hertz andCDC-link is the input capacitance In such conditions the converterrsquos maximumeffective switching frequency (f S(max)) should occur with no pulse-skipping With agiven primary MOSFET it is possible to estimate the charge stored in its parasiticoutput capacitance (QCOSS) from its datasheet using (41) Given that the same TNEG

will be used regardless of exact DC-link voltage an estimate of the average powerconsumed by discharging COSS from the highest possible DC-link voltage (VIN(max))is defined as

Pneg =12

QCOSSVIN(max) f S(max) (54)

Again this will only be a guiding under-estimate since constant COSS and zeroleakage inductance is assumed The total power (PIN) is the sum of the Prated thecircuit losses (Ploss) and Pneg

PIN = Prated + Pneg + Ploss (55)

By using the top-level specifications of output voltage (VOUT) and rated power alongwith the turns-ratio (N) desired maximum switching frequency and minimum inputvoltage ripple it is possible to calculate the required inductances by assuming theideal current waveforms Using fundamental equations it is possible to derive

L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)

The secondary inductance can then be found using the turns-ratio and (212)

41


Due to inevitable leakage inductance the actual magnetizing inductance will besmaller than the value given by (57) and therefore additional turn(s) should beadded to compensate Leakage inductance can be estimated using short and opencircuit tests [56 57] For a universal-input adapter low-line input voltage should beused for these calculations However f S(max) will occur with high line input due tothe smaller fixed ON-time

533 Start-Up Routine and Primary Logic

The secondary side controlled Flyback concept requires the output capacitor (COUT)to be charged before the turn-ON requests required for primary side ZVS are possiblethere must therefore be a method of charging COUT at start-up While any start-uproutine must necessarily be undertaken by the primary side due to the lack of outputvoltage it must be done without additional measurementcomputation to maintainvery simple primary side control ndash simple enough to be implemented with dedicateddiscrete logic It was assumed that the load is disconnected from the output capacitorat start-up via a load-disconnect switch as with the existing USB-PD controller shownin [58] Briefly stated

1 The primary side is connected to grid input voltage

2 The primary side sends low frequency pulses to charge COUT via S2rsquos bodydiode until secondary side ldquowakes uprdquo

3 Using the synchronous-rectification sensing the secondary side waits for theend of a charging pulse and then sends a negative current pulse putting theprimary side into ldquoslaverdquo mode

4 Steady-state control begins

Specifically as soon as COUT is charged beyond rated output voltage (Vrated) thecontroller connects to the load and takes responsibility for maintaining the outputvoltage This control transition occurs at Vrated so that the fixed negative currenttime is sufficient to achieve a zero voltage crossing on the primary side With activemeasurement of VOUT and continuous calculation of TNEG it would be possibleto begin secondary side control earlier as soon as VOUT is sufficient to power thecontroller However this was not implemented here

42


Fig 57 shows a flow chart of the start-up routine from the perspective of both pri-mary and secondary side The frequency of the initial charging pulses from theprimary side must be low enough to provide plenty of time to fit the first ldquohands-hakerdquo turn-ON request before the next pulse Once the secondary side controllerenters ldquosteady-staterdquo it follows the block diagram in Fig 56

Steady State Primary Slave Mode

Primary Side Secondary Side

Connect to Grid

Detect high orlow-line input

Send lowpower pulse

Wait

gggggggggggggVDS(S1) lt 0 Vsensed

N

Y

Send highpower pulse

Wait

Sample VOUT

gggggggggggggVOUTgt Vrated

N

Y

Wait for endof sync-rec

Send turn-ONrequest

gggggggggggggSync Recsense OK

N

Y

Enter Steady State


Y

Figure 57 Flow chart of primary start-up routine with secondary side response

43


54 65 W Demonstrator Hardware ndash SSCF1

A 65 W prototype was built to demonstrate the Secondary Side Controlled Flybackconcept It was designed to supply 20 VDC output with a maximum switchingfrequency of 270 kHz This specific prototype is herein referred to as ldquoSSCF1rdquo ndashSecondary Side Controlled Flyback 1 This section briefly describes the constructionof the coupled inductor the chosen prototyping control boards and the power board

541 Control Boards

For prototyping purposes and to easily experiment with primary switching timesboth controllers were based on external control boards with an FPGA used to processprimary side double-pulse requests rather than dedicated discrete logic Tab 51lists the two control boards used The FPGA board was operated with a 27 MHzclock introducing 37 ns of additional delay to primary side turn-ON

Table 51 External control boards for SSCF1

Primary Side LATTICE iCE40-HX8K FPGASecondary Side INFINEON XMC4500 Relax Lite

The XMC4500 incurred a synchronous rectification turn-ON delay of up to 81 ns(although this is relatively inconsequential since current can conduct through S2rsquosbody diode) The overall delay for turn-OFF was 35 ns creating a small pulseof negative current of asymp minus255 mA (minus45 mA on primary side) at the end of eachsynchronous rectification period Significant enough to incur non-negligible currentcirculation but far from enough to risk causing an unwanted S1 turn-ON command

Figure 58 INFINEON XMC4500 Relax Lite prototyping controller board

44



In general a Flybackrsquos coupled inductor corewinding arrangement should avoidsaturation have low leakage and incur minimal losses It is also preferable that theswitching frequency at low- and high-line is relatively similar A large turns-ratio(N) allows the use of secondary side MOSFETs with a lower voltage rating (generallylower device losses) but causes high-line switching frequency to rise further awayfrom low-line The effect of turns-ratio on total switching period can be seen in thederived equation (58)

1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)

Using MATLAB [59] and GeckoCircuits simulation software [60] a turns-ratio ofN = 5 was found to offer a good balance between frequency range and losses [5960] By using (56) to find the inductances required for 270 kHz operation anddetermining peak currents and flux densities an appropriate core shapesize couldbe found as shown in Tab 52

Table 52 Key parameters of SSCF1 coupled inductor

Parameter Symbol Value

Turns-Ratio N 5 (153)Primary Inductance L1 77microH

Secondary Inductance L2 31microH

Low-Line Peak Currents IL1 IL2 41 A 205 AHigh-Line Peak Currents IL1 IL2 39 A 196 A

Core ShapeMaterial ndash RM10i 3C95Air gap lg 300microm

Winding Type pri sec litz foilWinding Arrangement inn out 15 3

To see whether the Secondary Side Controlled Flyback concept could be used onthe most rudimentary power boards a simple two-layer winding arrangement waschosen for the coupled inductor (although litz wire was used for the primary windingto help reduce winding loss)

45


543 Power Board

The SSCF1 power board used the components listed in Tab 53 and the assembledboard is shown in Figs 59 and 510 The large loops were included to easily measureprimary and secondary inductor current but could be short-circuited when notneeded ndash minimizing stray inductance Excluding the loops the boxed dimensionswere 30 cm times 65 cm times 23 cm which equals 442 cm3 (27 inch3) Excluding the inputemi-filter the resulting power density was 147 Wcm3 (23 Winch3)

Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link

Current Measurement Loops

Figure 59 65W demonstrator SSCF1 Dimensions 30 cm x 65 cm x 23 cm

Table 53 Key parameters and components of the SSCF1 power board

Input Capacitance CDC-link 110microFOutput Capacitance COUT 400microF

Primary MOSFET S1 CoolMOS P6 255 mΩ ThinPAK 8x8Secondary MOSFET S2 OptiMOS 5 35 mΩ (100 V) SuperS08

Gate Driver - Infineon Eice 2EDN7524F

46


S1Driver

Diode Bridge

VDS(S1)SensingVDS(S2)

Sensing

S2Driver

Snubber Diode

AdditionalCOUT

Figure 510 SSCF1 back side

Tab 54 lists the snubber parameters (see Fig 25) required to ensure that the peakVDS(S1) overshoot (due to L1 leakage inductance) remained below the voltage ratingof S1 The employed values were first estimated via analytic calculation and werethen refined empirically

Table 54 RCD snubber components for SSCF1

Resistance RSn 15 kΩCapacitance CSn 64 nF

Diode DSn IDP08E65D1 (650 V)

An additional EMI-filter board was made to provide differential and common modenoise suppression to satisfy the Class B SMPS requirements [61ndash63] Due to thevariable frequency control scheme the filter was required to provide significantdamping across a range of switching frequencies ndash mandating a large filter [6465] The final filter volume was 403 cm3 (246 inch3) The total converter volumewas 845 cm3 (516 inch3) resulting in an overall power density of approximately077 Wcm3 (126 Winch3) The large EMI-filter is a drawback of the variable fre-quencyCOT approach

The various DC voltages required for the gate drivers comparators and sensingreferences were derived from a single 15 V bus using a combination of on-boardDC-DC converters and resistive dividers

47


544 Sensing ndash Passive Component Parameters

Tab 55 lists the components used for the drain-source voltage sensing sub-circuitsshown in Fig 51 and Fig 53

Table 55 Key components for SSCF1 VDS sensing

High Voltage Diode D1 MURS160T3G (600 V)Voltage Source Diode D2 DA221FHTL

Zener Diode D3 MM3Z47T1G (47 V)

High Voltage Capacitor C1 3 pFLow Voltage Capacitor C2 60 pFComparator Protection R1 10 kΩ

Current Limiter R2 500ΩDC Voltage Source U1 50 V

Pri amp Sec Comparator - ADCMP600

Sec Current Limiter R3 56 kΩSchottky Diodes D4 D5 B340A-12-F (40 V)

The capacitances C1 and C2 include the estimated parasitic capacitances of the high-voltage diode and zener diode respectively Ie zener diode capacitance plus C2 =

60 pF The resistor R2 was dimensioned with (51) assuming a 5 V source for U1 andusing the datasheet for S1 listed in Tab 53 In order to reduce current through thesecondary side comparatorrsquos parallel zener diodes the resistor R3 was chosen to beas large as possible without noticeably slowing sensing response time Tab 56 liststhe components used for the output voltage sensing in Fig 54

Table 56 Key components for SSCF1 VOUT sensing

Resistive Divider R4 60 kΩResistive Divider R5 15 kΩ

Comparator - ADCMP600DC Voltage Source UREF 40 V

48

55 Experimental Results


This section focusses firstly on the feasibility of the secondary side Flyback controllerwith zero voltage primary turn-ON and secondly on the corresponding operatingconsequences of using COT control with the proposed concept The followingmeasurements of the SSCF1 prototype are presented in this section

bull Steady-state COT operation

ndash High- and low-line behaviour (230 VRMS and 120 VRMS)

ndash Frequency and power limit

ndash Switching frequency vs output load

bull Primary side drain-source voltage sensing

ndash Propagation delay vs opto-isolators

ndash Autonomous zero crossing blanking


bull Converter efficiency measurements and loss analysis

ndash Efficiency for both high- and low-line input voltages

ndash Component loss breakdown and suggested improvements

551 Steady-State COT Operation

Both high- and low-line input voltages were tested between 10 and 100 ratedload (and beyond into overload conditions) This section gives the fixed primaryON-time (TON) and turn-ON request time (TNEG) used in each case as well as selectedmeasurements of steady-state operation and the switching frequency range for eachload point

High-Line Input Voltage

High-line steady-state operation was tested using 230VAC input voltage and withthe fixed primary ON time (TNEG) and negative current pulse time (TON) shown inTab 57 A 12 larger ON-time was used than calculated with (52) due to lossesand leakage inductance

49


Table 57 Fixed switching times for steady-state COT high-line operation

Secondary Negative Current Time TNEG 070microsPrimary ON-time TON 085micros

Fig 511 shows a measurement of primary drain-source voltage and secondary sideinductor current during steady-state operation at high-line The measurement istaken at 70 load at the peak of the DC-link ripple resulting in a switching frequencyof 175 kHz and a peak inductor current of 4 A and 20 A for primary and secondaryside respectively The negative current on the secondary side required to dischargethe chosen primary MOSFET in such conditions was minus42 A ndash a relatively largecurrent equating to minus900 mA on the primary side

106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)

mdash VDS(S1)mdash iL2

Figure 511 Measured VDS(S1) and iL2 in high-line steady-state COT operation

The secondary side controller does not monitor the input ripple and therefore thesame peak negative current was used throughout the entire AC grid period regard-less of exact DC-link voltage and energy stored in COSS(S1) For a given output loadand DC-link voltage the binary output voltage sensing determines the switchingfrequency by indicating when the next switching cycle should begin

50


For example at t=116micros in Fig 511 the secondary inductor has de-energizedand the controller refrains from sending the subsequent negative pulse indicatingthat VOUT exceeds the 20 V threshold and the control has re-entered twait for pulse-skipping At t=1179micros the turn-ON request is sent indicating that VOUT fell belowits reference value and the VOUT comparator signal has fallen low

With sufficient COUT the output ripple is mainly dependent on the sensitivity ofthe output voltage sensing and the speed of the controller To a lesser extent it is de-termined by the peak inductor currents and negative current pulse A measurementof output ripple for high line corresponding to Fig 511 is shown in Fig 512 Thepeak ripple was found to be 282 mV (14 of mean VOUT)

0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2

Figure 512 Measured VOUT and iL2 in high-line COT steady-state operation

Low-Line Input Voltage

Low-line tests used 120VAC input and thus employed a larger TON and smaller TNEG

as shown in Tab 58 Though the negative current pulse is smaller for low-lineoutput voltage ripple was almost identical to high-line because of the increasedON-time Peak low-line output voltage ripple was 301 mV (15 of mean VOUT)

51


Table 58 Fixed switching times for steady-state low-line COT operation


Device Stresses

To give an impression of device stress Tab 59 lists the ldquoworst-caserdquo blocking volta-ges and drain currents for primary and secondary switches The peak VDS valuesare measurements of the overshoot peak after each switchrsquos respective turn-OFF

Table 59 Maximum blocking voltages and drain currents for S1 and S2

S1 S2 Occurs during

Peak VDS 532 V 869 V Peak DC-link voltage at high-lineRMS VDS 345 V 368 V High-line input at full output loadMean VDS 308 V 201 V As above

Peak Id 410 A 205 A Peak DC-link voltage at low-lineRMS Id 119 A 673 A Low-line input at full output loadMean Id 071 A 366 A As above

Outside of the specific conditions specified in Tab 59 the blocking voltages anddrain currents during steady-state are smaller and dependent on the input linevoltage and input voltage ripple and indirectly by the output load

Frequency Limit and Synchronous Rectification

Each fixed primary ON-time for high- and low-line was chosen to support full loadfor any DC-link voltage within the expected input ripple range It follows thatwithin rated power some pulse skipping will always occur However Fig 513shows a measurement taken above 100 output load whereby no pulse skippingoccurred at the minimum point of the input voltage ripple It shows drain-sourcevoltages for two low-line switching periods along with two secondary side controlsignals synchronous rectification comparator output and S2 gate-drive signal Bet-ween t =155micros and t = 315micros comparator output is high indicating that the currentthrough S2 is positive and that synchronous rectification is ongoing

52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)

mdash VDS(S1)mdash VDS(S2)mdash Gatemdash QSR

Figure 513 VDS sync rec sense and S2 gate signals in overload conditions

Afterwards the comparator output goes low indicating that current is now negativebut S2 is then kept ON for the fixed time (TNEG) with zero twait to immediatelytransition into a negative current for a turn-ON request When no pulse-skippingoccurs the converter is operating at its power and switching frequency limit ndash noadditional power can be delivered with the fixed ON-time and VOUT will drop

With timings optimized for rated output power and healthy grid voltage thiszero wait period will occur at minimum expected input voltage ripple and 100 load However it follows that in the event of unexpected low grid voltage opti-mized timings will not be able to provide stable output voltage at 100 load Tocompensate for a low grid voltage and maintain very simple primary side logicwith constant ON-time the ON-time must be oversized for regular operation ndash asignificant disadvantage of the COT approach

53


Variable Switching Frequency Range

The COT approach was chosen because it allows the primary logic to remain verysimple allowing as much control to move to the secondary side as possible Ho-wever for a given load such a constant primary ON-Time necessarily leads tovariable switching frequency that drifts with the input voltage ripple as explainedin Section 53

Using the switching times specified in Tabs 57 and 58 the maximum and mini-mum switching frequencies were measured for high- and low-line Fig 514 showsthe range of switching frequencies in each case for 10-100 load This resulted in thepeak low-line switching frequency to be slightly below the 250 kHz desired maxi-mum calculated with (58) due to the slightly increased ON-time used to compensatecircuit losses

20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro

s)ON-time (120 VRMS)ON-time (230 VRMS)

Max Freq (120 VRMS)Min Freq (120 VRMS)Max Freq (230 VRMS)Min Freq (230 VRMS)

Figure 514 SSCF1 Switching frequency and primary ON-time vs output load

The range of switching frequencies is proportionally much larger for high loadsdue to the larger input voltage ripple At full load there is a difference of morethan 100 kHz for both high- and low-line input As the output load decreases theswitching frequency range and magnitude also decrease due to the ever-increasingwait time between turn-ON requests This caused low-line operation with 10 loadto be below 20 kHz and audible

54


Such a wide range in switching frequency severely limits the optimization of thecoupled inductor design (core material air gap ) since the fixed ON-time mustbe large enough to support full load at the lowest input voltage ripple meaningthat peak inductor current is very high at the peak of the input voltage ripple Thisfurther exacerbates the amount of pulse-skipping for low loads due to the smallerinput voltage ripple ndash leading to an even lower switching frequency As predictedby (58) high-line operation yielded slightly higher switching frequencies acrossthe load range (due to larger input voltage and the reduced primary ON-time) butremained within the same general order of magnitude as with low-line (due to theincreased negative current time)

552 Primary Side Drain-Source Sensing Behaviour

The primary side drain-source sensing is a critical part of proving the feasibility ofthe proposed opto-isolator free communication Measurements of the double-pulsesensing operating under high- and low-line can be seen in Fig 515 and Fig 516 withthe initial pulses (caused by the steep VDS slope) occurring at tasymp155micros and tasymp095microsrespectively Overall sensing reliability has been demonstrated through continuoussteady-state operation but it is also important for the primary side sensing to berobust in terms of unwanted zero voltage crossings and to be competitive withopto-isolators in terms of ldquopropagation delayrdquo

Primary Side Turn-ON Delay

A conventional primary side controller communicates to the synchronous rectifica-tion switch via an opto-isolator or magnetic coupling Likewise a secondary sidecontroller would communicate to the primary switch in the same way For the propo-sed strategy to compete with existing secondary side approaches the delay betweenthe zero crossing and subsequent S1 turn-ON should be less than the propagationdelay of a modern standard opto-isolator (70-150ns) and it should compete with fastdigital opto-isolators (25-50ns) [66 67] As seen in Figs 515 and 516 the total delaybetween the drain-source zero voltage crossing of S1 and the subsequent gate signalinto the driver was measured to be 71 ns at high-line and 75 ns at low-line inputvoltage Importantly the FPGA clock causes 37 ns of this delay meaning that theactual circuit delay is 34 ns and 38 ns for high- and low-line respectively

55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)

mdash VDS(S1)mdash QPRImdash Gate

Figure 515 Demonstration of primary side VDS sensing at high-line

1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)


Figure 516 Demonstration of primary side VDS sensing at low-line

56


These measurements indicate that this sensing approach is indeed able to outperformmost and match the delay of the fastest opto-isolators If the gate-driver propagationdelay and MOSFET turn-ON time are also included this prototype achieved anoverall delay time of asymp112 ns which is almost as fast as standard opto-isolatorsalone Tab 510 lists a breakdown of primary turn-ON delay

However these measurements also reveal a limitation In Fig 516 the total delaybetween the end of the turn-ON request and primary zero voltage crossing is 395 nsThis time is determined by the magnitude of negative current and S1rsquos parasiticoutput capacitance This limits the approach in very high switching frequencyapplications ndash 395 ns would be very large for a 10 MHz converter with a switchingperiod of just 1micros Increasing the negative current would reduce this time butreduce efficiency and consume more of the available duty cycle Another optionwould be to use a device with significantly smaller output capacitance

Table 510 Primary side sensing and turn-ON delay times

Delay Times (ns)Source Low-Line High-Line

Sense Circuit 34 30Comparator 4 4

FPGA 37 37

Total Signal Delay 75 71

Driver Propagation 20 20Turn-ON Time 18 20

TOTAL 113 111

Flyback Ringing Blanking

To test the autonomous filtering of false turn-ON signals the input voltage wasreduced to force the primary Flyback voltage to cross 0 V after primary turn-OFFFig 517 shows the primary controlrsquos response in such conditions No gate signalis generated at t=75micros despite the definite zero crossings of VDS(S1) observed Thedvdt across S1 prior to the zero crossing is insufficient to trigger the comparator andthus the primary control only receives a single pulse ndash no gate signal is generatedand S1 successfully remains OFF

57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)


Figure 517 Demonstration of blanked zero voltage crossings in Flyback ringing

553 Start-Up Routine

Measurements of the start-up routine described in Section 533 with low-line inputvoltage are presented here The primary side was programmed to execute 25 kHzcharging pulses with an ON-time of 550 ns resulting in peak primary inductorcurrent of approximately 12 A Using such a small frequency and ON-time providesplenty of space for the secondary controller to deliver its initial handshake turn-ONrequest after rated voltage has been achieved Fig 518 shows the end of the chargingphase at tasymp142 ms and the fall of the output voltage to the minimum value until thesecondary side takes control and connects the output load at tasymp154 ms

A close-up view of the handshake turn-ON request is shown in Fig 519 Aftersufficient output voltage is sensed the secondary controller uses the synchronousrectification sensing to wait until the secondary inductor is de-energised (end ofsynchronous rectification) It then sends a ldquohandshakerdquo turn-ON request to theprimary side As soon as the forced zero voltage crossing is detected across S1 theprimary side enters ldquosteady-staterdquo halting the 25 kHz charging pulses and returninga single full-power pulse before waiting for the next turn-ON request

58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)

mdash VDS(S1)mdash VOUT

Figure 518 Measurement of proposed start-up routine with low-line input voltage

14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo

Synchronous Rectification

t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)

mdash VDS(S1)mdash GateSEC

Figure 519 Annotated close-up of end of proposed start-up routine

59


554 Efficiency Measurements

The SSCF1 demonstrator was built to show the proposed concept as a feasible andworkable control strategy with efficiency as a secondary concern Nonetheless thissection briefly discusses efficiency measurements taken from the SSCF1 demonstra-tor and how to improve the results to match current state-of-the-art For contexta target efficiency is taken from the PMP9208 power adapter reference design fromTexas Instruments Inc [37] This professional Flyback demonstrator has the samerated output power (65 W) and a similar output voltage of 195 V (rather than 20 V)

0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()

High-line (SSCF1) (meas)Low-line (SSCF1) (meas)

High-line (PMP9208)Low-line (PMP9208)

High-line (SSCF1) (calc)

Figure 520 Measured and calculated SSCF1 efficiency against PMP9208

The PMP9208 uses a more conventional UCC28630 primary side regulation controllerand conveniently uses the same coupled inductor core shape (RM10i) however thecore materials are different (3C96 rather than 3C95) [68] Input and output powerwere measured at multiple load points using a ldquoNorma-5000rdquo power analyzer andwith both high- and low-line input voltage (230 and 120 VRMS respectively) [69]Fig 520 shows the efficiency based on these measurements as well as that of thePMP9208 The SSCF1 exhibited significantly poorer efficiency than the referencedesign especially at low load The following analysis shows however that thiswas mostly due to the construction of SSCF1rsquos coupled inductor rather than a directconsequence of the control scheme

60


555 Loss Breakdown

Fig 521 shows a breakdown of the main losses for the SSCF1 demonstrator ope-rating under high-line input voltage Following the same approach specified in[70] the individual loss contributions were calculated using a combination of ana-lytic methods and simulation The corresponding calculated efficiency is shownin Fig 520 alongside the measured values showing an over-estimated but reaso-nable match The loss breakdown for low-line input voltage is not presented heresince each contribution is broadly similar to that of high-line and does not alter thefollowing analysis

556 Effect of Proposed Secondary Side Control on Efficiency

The proposed concept (sending turn-ON requests from secondary side to the pri-mary side switch via the coupled inductor) incurs additional device losses whengenerating the negative current pulse requests However Fig 522 shows that theloss contribution from the corresponding sources (S2 conduction gate turn-ON andturn-OFF loss) are relatively small and are not responsible for the poor efficiencySome of these additional losses are also offset by the synchronous rectification andzero voltage primary turn-ON features offered by the Secondary Side ControlledFlyback

557 Effect of Non-Optimal Coupled Inductor on Efficiency

The two largest loss contributions (accounting for asymp 62 of losses) are snubber lossand core loss The former caused by dissipating the energy stored in the leakageinductance at primary turn-OFF and the latter caused by hysteresis and eddy currenteffects [71] The magnitudes of these contributions are determined by the coupledinductor and not by the Secondary Side Controlled Flyback concept nor directlyby the COT control scheme By contrasting the two coupled inductor designs it ispossible to estimate how the demonstrator efficiency might compare to the referencedesign if the core material and coupling factor were identical

61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore

WindingDiode BridgeS1 turn-OFFS2 turn-OFFSec Sense

Other

Figure 521 Overall loss breakdown for SSCF1 in high-line operation (calculated)

10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate

S1 turn-ONS1 body diode


S2 condS2 gate

Figure 522 Breakdown of loss contributions labelled as ldquoOtherrdquo in Fig 521

62


Leakage Inductance

The snubber loss shown in Fig 521 represents the leakage energy dissipation re-quired to keep the primary voltage overshoot safely below the rated voltage of theprimary switch (600 V) The primary side leakage inductance of SSCF1 was me-asured and is shown in Tab 511 along with the resulting coupling factor RCDsnubber parameters are given in Tab 54 A coupling factor (k) of 0963 representsconsiderably inferior coupling than for the reference design which had a couplingfactor of 0984 As well as winding type and core shape winding arrangement is animportant factor The SSCF1 used a simple non-interleaved arrangement wherebythe entire primary winding was surrounded by the entire secondary foil windingIn contrast the reference design was interleaved with the primary wound on bothsides of the secondary foil ndash a reliable method of reducing leakage [72]

Table 511 Measured leakage inductance and coupling factor for SSCF1

Primary Inductance L1 770microHPrimary Leakage Inductance L1

σ 284microH

Coupling Factor k 0963

Core Material

By repeating the core loss calculation using the 3C96 material used in the referencedesign instead of the 3C95 the core loss reduces significantly For example at 100 load the core loss would fall from 302 W to 237 W

Modified Loss Calculation

Replacing the SSCF1 demonstratorrsquos core material and coupling factor with thatof the reference design shows a calculated efficiency improvement of asymp4 acrossthe load range bringing it much closer to the PMP9208 reference efficiency ndash seeFig 523 Even though any actual measured efficiency of the demonstrator willlikely be less than calculated these results suggest that the non-optimal coupledinductor design of SSCF1 was a key limiting factor to the demonstratorrsquos efficiencyThe loss breakdown for the modified SSCF1 demonstrator in Fig 524 shows reducedsnubber loss and an improved balance between core and winding loss

63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()

High-line (SSCF1) (meas)High-line (PMP9208)

High-line (SSCF1) (calc)NEW High-line (SSCF1) (calc)

Figure 523 Comparison of simulated and measured efficiency of SSCF1 using ori-ginal and modified transformer versus PMP9208

10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other

Figure 524 Loss breakdown assuming coupled inductor core material 3C96

64

56 Conclusion

558 Effect of COT Control on Efficiency

The peak currents and switching frequencies resulting from the COT control schemealso increased losses in the coupled inductor and elsewhere in the circuit The COTscheme requires a fixed ON-time that at the minimum DC-link voltage can supportthe rated load Subsequently for all other conditions (especially at low load) the peakinductor currents are rdquoover-sizedrdquo leading to larger turn-OFF core and winding lossthroughout steady-state operation ndash compounding the large loss contributions fromthe non-optimal coupled inductor Furthermore the variable frequency operationarising from COT makes it difficult to optimise the coupled inductor and to selectthe switching devices (balancing conduction and gate loss) These effects suggestthat the secondary side controlled Flyback concept would benefit from a variableON-time control to achieve constant (or at least reduced) switching frequency

56 Conclusion

This chapter aimed to demonstrate the feasibility of the Secondary Side ControlledFlyback concept in hardware by proving a reliable cross-isolation communicationmethod without opto-isolators a workable start-up routine and a steady-state con-trol scheme than can regulate the output voltage

Firstly the primary side switch was successfully controlled from the secondaryside through the coupled inductor via zero crossings of its drain-source voltage Theproposed primary-side VDS sensing protected the sensing circuitry from the largedrain voltage and autonomously distinguished unwanted zero voltage crossingsthat may occur due to Flyback ringing during wait periods from genuine primaryturn-ON requests from the secondary side This helps the primary side logic staysimple independent and reliable The primary side sensing delay was found to beas low as 34 ns twice as fast as the typical propagation delay of a quick modernopto-isolator However the time required to discharge parasitic capacitance of asuper-junction MOSFET to 0 V limits the application of this technique to sub-MHzapplications

Secondly the proposed start-up routine was also proven and demonstrates thefeasibility of charging the output capacitor using the independent primary sidelogic before the main secondary side controller wakes up

65


Thirdly steady-state operation with variable frequency ZVS operation has beendemonstrated at high- and low-line input voltage with asymp20-250 kHz switching fre-quency for a 65W load The COT control scheme achieved stable output voltagewith ripple less than or equal to 15 of mean output voltage and offered naturalcurrent limiting in overload conditions However the control scheme also addsconstraints to the design of any input emi-filter or Flyback coupled inductor sincethey must be able to handle both the highest frequencies and the large peak currentsat low frequency

All of the main disadvantages of the proposed concept come from the switchingfrequency rangelimit caused by COT and the large negative current needed forfull primary ZVS The large peak inductor currents resulting from COT also harmsefficiency especially at low-load To develop a more viable implementation of theSecondary Side Controlled Flyback concept these issues can be solved by adaptingthe existing approach with two key changes

bull Variable S1 ON-time for constant switching frequency

bull Quasi-ZVS for S1 turn-ON commands

66

Chapter 6

Improving the Viability of theSecondary Side Controlled Flyback

61 Chapter Outline

By addressing the conclusions drawn from the SSCF1 prototype in Chapter 5 thischapter presents work intended to improve the viability of the Secondary Side Con-trolled Flyback concept

It begins with Section 62 whereby a new primary side VDS(S1) sensing appro-ach for quasi-zero-voltage switching (Q-ZVS) operation is presented that maintainsthe advantages of the previous double-pulse proposal Section 63 then presents anovel lossless ground-referenced synchronous rectification sensing circuit that pro-vides fast zero-current crossing detection with lt45 ns delay Afterwards Section 64describes a modified primary side control approach that achieves stable switchingfrequency across the load range and reduces peak inductor currents Section 65describes the improved demonstrator hardware and gives a guide for dimensioninginductances and switching times for this new control scheme and for minimizingleakage inductance Finally Section 66 presents measurements of this demonstratorincluding

bull The response of the proposed VDS sensing upgrades

bull The proposed control scheme during steady-state and step load changes

bull Measured efficiency for 120 VRMS and 230 VRMS input voltage

bull An analysis of switching frequency stability over the load range

67

Chapter 6 Improving the Viability of the Secondary Side Controlled Flyback

62 Q-ZVS Improvement

Fig 61 shows a sketch of a turn-ON request where a positive voltage crossing isemployed to command S1 to turn-ON rather than a zero-voltage crossing Thisresults in Q-ZVS In comparison to the ZVS technique described in Section 44discharging COSS(S1) down to a positive voltage requires less negative current fromthe turn-ON request At the cost of increased S1 switching loss Q-ZVS yields twomain benefits for the secondary side controlled Flyback approach

bull Reduced current circulation for turn-ON requests reducing MOSFET con-duction loss and freeing duty cycle space for positive power transfer

bull Reducing S2 switching loss turn-OFF overshoot and secondary side EMI

gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS

Figure 61 Sketch of Q-ZVS turn-ON request with sense and gate signals

68


621 Calculation of Negative Current Time

The peak secondary side negative current (INEG) and corresponding S2 ON-time(TNEG) required to reliably push VDS(S1) down to VQZVS can be calculated with know-ledge of the basic Flyback converter parameters and the parasitic output capacitanceof S1 A detailed explanation of this calculation is given in Section 44 for the caseof forcing zero voltage crossings The same approach is summarized here adaptedfor positive Q-ZVS threshold crossings instead Firstly an estimate of the chargerequired to discharge COSS(S1) to VQZVS from the initial drain-source voltage (VDS) canbe found using (61)

QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)

Disregarding oscillations VDS is equal to the DC-link voltage plus the reflectedoutput voltage as shown in (62) where N is the turns-ratio between L1 and L2Secondly the peak secondary side current required to achieve this discharge ofCOSS(S1) can be found using (63) along with the corresponding secondary ON-time(TNEG) using (64)

VDS = VDC-link + (N VOUT) (62)

INEG =

radicQCOSSVDS N2L1 (63)


This estimate for TNEG should be treated as a minimum guide-line since leakageinductance power loss and switching oscillations are not considered A method ofdimensioning the slope-detection circuit to respond adequately to the slope resultingfrom this negative current pulse is discussed in Section 622 An essential featureof the Secondary Side Controlled Flyback concept is that VDS(S1) is manipulated bythe secondary side controller to control S1 Stable and reliable sensing of VDS(S1) istherefore critical to the viability of the concept Furthermore accurate sensing of S2

drain current is needed to execute the synchronous rectification feature promised bythe secondary side based controller The drain-connected sensing circuits developedto achieve this are presented here including a precise and lossless synchronousrectification upgrade The exact component parameters are given in Tab 65

69


622 Primary Side Drain-Source Voltage Sensing

To enable Q-ZVS based turn-ON requests and maintain the safety of the double-pulseapproach from SSCF1 the primary side sensing looks for instances of very steepVDS(S1) slope (indicating a genuine turn-ON request) and when VDS(S1) has fallenbelow the Q-ZVS voltage threshold Two simple parallel comparator networks arepresented each responsible for one such sensing signal

Fig 62 shows a schematic of the propsoed Q-ZVS threshold sensing circuit Thevoltage at the comparatorrsquos inverting input is a scaled reflection of VDS(S1) thatdepends on the ratio between C3 and C4 The large resistors R6 and R7 ensure thesame scaling in cases of DC VDS(S1) Once this voltage falls below the fixed referenceUq the signal Qqzvs goes high

C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6

Figure 62 Schematic of circuit for detecting quasi-ZVS threshold crossings

Fig 63 shows the slope sensing circuit It is comprised of a fixed offset voltagesource Uslope along with a small RC combination to form a simple high-pass filter

R8

C5

minus+

minus

+

Qslope

UslopeS1

Figure 63 Schematic of primary VDS slope sensing circuit

70

63 Synchronous Rectification Improvement

Qslope goes high whenever the dVDS(S1)dt caused by a turn-ON request is sufficientto cause negative current through C5 a derived equation for this is

C5d VDS(S1)

dtgt

Uslope

R8(65)

Parallel Signals ndash Double Pulse

As before the primary side logic looks for a genuine turn-ON request made up oftwo distinct yet consecutive pulses However each component of this double pulsenow comes from the two separate comparators shown in Figs 62 and 63


The synchronous rectification sensing must detect the instant the body diode of S2 be-gins conducting and the instant inductor current has fallen to 0 A Fig 64 shows theproposed circuit which comprises a RC filter (R9 and C6) and a protective low-powerMOSFET (SSF) connected to S2rsquos drain The gate of SSF is connected to the supplyvoltage of QSR to create a source-follower effect whereby SSF only conducts whenVDS(S2) falls below the supply voltage minus SSFrsquos gate-source threshold voltage

R9

C6

minus

+

minus

+

S2

SSF

QSR

USF


SSF protects QSR from high VDS(S2) with almost zero conduction loss through R9 as C6

can be very small In practical terms USF should be the supply voltage for QSR WithSSF protecting QSR instead of the parallel diodes the proposed circuit does not requiresuch a large R9 reducing sensing delay to tens of nanoseconds Beneficially thissolution requires only one comparator and uses secondary side ground as the fixedcomparator reference in contrast to existing solutions that require an additionalvoltage reference and hysteresis op-amp [73]

71


64 Variable-ON-Time Control

641 Proposed Concept

The novel variable ON-time control (VOT) scheme proposes adding a counter tothe primary side logic to measure the frequency of turn-ON requests ( f R) Thenf R can be compared to a reference frequency (FREF) to infer whether a change inthe ON-time (tON) is necessary to maintain constant switching frequency ( f S) Egdecreasing tON when f R is lower than f REF will cause the synchronous rectificationtime and twait to decrease and f S to rise back towards FREF This results in a splitcontrol structure with the primary side independently helping the secondary sideFig 65 shows that for a given load maintaining constant f S keeps peak inductorcurrents constant despite DC-link ripple To see the controllerrsquos effort to graduallychange the peak inductor current the more transparent current trace is included andshows the current from the preceding switching period

tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts

Figure 65 VOT control response to rising DC-link voltage

72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired

Figure 66 Effect of increasing output load on twait and VOT response

Modulating tON for constant f S also causes power flow to match the output loadautomatically without direct feedback Eg for an increasing load (Fig 66) twait

will decrease due to the steeper VOUT discharge slope causing f R to rise IncreasingtON will simultaneously compensate this frequency rise and supply more power tosupport the load While tON is rising it is vital that an upper ON-time boundary(TUPPER) exists to avoid core saturation or excessive VDS(S1) overshoot Importantlythis same TUPPER should align with rated power circuit parameters and chosen FREF

such that at full-load twait reduces to almost 0 s A sketch of this scenario is shownin Fig 67 The minimum TUPPER required to supply sufficient power in this waycan be calculated with (66) and depends on peak DC-link ripple desired switchingfrequency and primary inductance ndash all of which are defined in Section 644

73


Beneficially TUPPER also ensures natural output current limiting during overload Insuch circumstances twait will fall to zero leading to a f S higher than Fref Howeverthe primary side will be unable to supply more energy per switching period thanthe upper ON-time limit TUPPER allows This will result in falling VOUT and limitedoutput current This is the same advantage offered by a constant ON-time controlbut now the limit is defined by the upper ON-time boundary rather than the fixedON-time

gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait

TUPPER TUPPER TUPPER

Figure 67 Operational effect on twait for full output load defined by TUPPER

TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)

Following the same approach as many existing Flyback converters a conventionalPI control structure was used for the VOT controllerrsquos modulation of tON [74 75]The error signal for the control loop came from comparing the measured switchingperiod to the reference switching period

74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R

Figure 68 Simplified diagram of implemented primary side control loop

642 Split Control Structure

The VOT scheme introduces a subtle change to the proposed control structure Theprimary side is now not only a slave to the turn-ON requests with a fixed responseit now is responsible for switching frequency regulation The combination of theindependent switching frequency and output voltage regulation naturally results inoutput power regulation Fig 69 shows a diagram of the new control structure

S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Output VoltageRegulationSwitching Freq

Regulation

Figure 69 Schematic showing split regulation responsibilities resulting from VOT


The start-up routine shown in Section 532 is still applicable to the VOT concept Assoon as VOUT is sufficiently high a turn-ON request is sent back to the primary sideputting the primary side into slave mode whereupon VOT operation begins

75


644 Calculating Inductances for VOT Control

Theoretically this VOT control scheme is not limited to any specific range of swit-ching frequencies However the choice of desired switching frequency has severalimplications on the overall Flyback circuit parameters the choice of switching de-vices and the dimensioning of the novel VDS sensing circuits described in Secti-ons 62 and 63 In particular it is critical to dimension the coupled inductor tosupply full rated power with the upper primary ON-time limit (TUPPER) at the lo-west expected DC-link voltage (minimum point of the input ripple (VDC-link(min)))This process matches that used to dimension the coupled inductor for COT controlbut now the switching frequency is lower and constant For convenience the sameequations are repeated here By calculating the power transfer in one grid period itis possible to calculate VDC-link(min) for a given DC-link capacitance (CDC-link)


2minus

POUT

CDC-link f grid(67)

where VRMS is the RMS grid input voltage and f grid is the grid frequency in hertzNext it is important to estimate the maximum steady-state power required of theconverter (PIN) This is the sum of the rated power (Prated) plus the circulating powerused to achieve the turn-ON requests (Pneg) plus the losses (Ploss)

Pneg =12

QCOSSVDC-link(max) f S (68)


Accurately knowing Ploss before constructing the converter is difficult but an estimatecan be found using simulation or analytic methods [76ndash78] A value for the primaryinductance (L1) can then be found iteratively using

L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)

N should be chosen based on desired VOUT S2 voltage rating and loss analysis [79]It can then be used to calculate the secondary inductance (L2) corresponding to L1

76



651 150 kHz Power Board

Measurements of VOT operation were made using the SSCF2 an improved demon-strator with improved PCB layout and winding arrangement for low losses andsnubber-less operation (see Fig 610 and Tab 61) The SSCF2 was designed to ope-rate at 150 kHz converting 120 VRMS 230 VRMS AC input to 20 VDC with a rated powerof 65 W Overall volume including the EMI-filter is 670 cm3 (409 inch3) a 21 vo-lume reduction from SSCF1 resulting in a power density of 097 Wcm3 (159 Winch3)

Coupled Inductor

S2

Secondary Side

COUT

Primary SideCDC-link

Input EMI-Filter


Connections toSecondary Controller

Figure 610 SSCF2 power board Dimensions 30 cm x 114 cm x 26 cm



Primary MOSFET S1 CoolMOS C7 125 mΩ ThinPAK 8x8Secondary MOSFET S2 OptiMOS 5 98 mΩ (100 V) SuperS08


77


652 Control and Adapter Boards

The SSCF1 demonstrator used a microcontroller based XMC4500 control board forprototyping the secondary side controller This introduced a synchronous rectifica-tion turn-ON delay of up to 81 ns due to signal processing time To reduce the S2

body diode conduction time due to this delay the secondary control was instead exe-cuted with an FPGA based prototyping board ndash where the signal processing delayis equal to the clock cycle

For prototyping purposes both primary and secondary side regulation and gatesignal generation were executed using an external FPGA demonstrator board ndash theLattice iCEblink40-HX1K The opto-isolator between the SSCF2 power board andprimary-side control board was used for safe initial sensing tests but was later re-moved All measurements presented herein were taken without such opto-isolatorsto minimize signal propagation delay

Power Board

AC InputConnections

OptionalOpto-isolators

Auxilliary Voltages

Secondary SideFPGA Board

Primary SideFPGA Board

Figure 611 Adapter board connecting control boards to SSCF2 power board

Fig 611 shows the complete prototyping set-up including an adapter board for shortsignal connections between power and control boards

To maintain isolation a separate control board was used for both primary and se-condary side ndash with the primary side responsible for switching frequency regulationvia VOT control and the secondary side responsible for output voltage regulationvia turn-ON requests The iCE40-HX1K was operated with a 33 MHz clock giving aperiod of asymp 33 ns

78



The chosen winding arrangement and core material should avoid core saturationwhile balancing core and winding losses in order to optimize size and loss [80] Fora meaningful comparison to the SSCF1 COT demonstrator the same turns-ratio of 5was chosen for the SSCF2 VOT demonstrator Furthermore a desired switchingfrequency of 150 kHz was chosen because it sits in the middle of the frequency rangeof the SSCF1 COT demonstrator and within the (upper) range of existing poweradapters

Tab 62 lists the inductances calculated using the methods described in Section 644as well as the components used

Table 62 Key parameters of new coupled inductor


Turns Ratio N 5 (204)Primary Inductance L1 107microH


Winding Arrangement inn mid out 5 4 15Winding Type pri sec pri litz foil litz


Peak Inductor Currents IL1 IL2 34 A 17 A

Measured Coupling Factor k 0994Peak Pri VDS Overshoot VDS(S1) 5792 V

This arrangement offered very high core window utilization and the primary andsecondary windings were measured to have a coupling factor of 0994 (measured at100 kHz) Conveniently the corresponding primary leakage inductance was foundto be low enough to avoid incorporating a snubber altogether the maximum pri-mary ON-time at peak DC-link voltage with 230 VRMS input voltage (asymp325 V) gavea peak VDS(S1) overshoot of 5792 V This is a significant improvement over the COTdemonstrator as snubber loss was the largest loss source 20 W at full load (31 )

79


654 EMI-Filter for VOT

The COT control scheme resulted in large inductor currents at a wide range ofswitching frequencies ndash see Fig 514 This mandated a physically large input EMI-filter [65] to satisfy the Class B SMPS noise requirements [63]

Tab 63 compares the filter volume for COT and VOT demonstrators both desig-ned for a rated output of 65W 20V Although in-rush currents are relatively largefor both control schemes due to the operation Flyback topology VOT only incursmaximum peak inductor current at maximum load (in contrast to COT where peakinductor current was independent from the load and varied only with DC-link rip-ple) VOT permits a physically smaller filter design as the damping can be focussedon a much narrower frequency range

Table 63 Input EMI-filter volumes for COT (SSCF1) and VOT (SSCF2)

Switching Frequency Boxed Volume

COT Control 15 kHz - 275 kHz 18 in3 295 cm3

VOT Control asymp 150 kHz 081 in3 133 cm3

Tab 64 lists the specifications of the VOT input filter along with the componentsused The VOT emi-filter can be seen on the SSCF2 power board annotated inFig 610 The inductances for both differential- and common-mode (CM) filters wereevenly split between both input lines for impedance balancing [62] Furthermore thedifferential-mode (DM) section was divided into three stages to reduce the overallvolume [64] and maximize power density

Table 64 emi-filter components and parameters

Parameter Value (no) (no) Core Capacitor

CM Inductance 320microH (x2) (1x) Vacuumschmelze W914CM Capacitance 99 nF (x2) (8x) Murata GA355QR7GF222DM Inductance 225microH (x6) (3x) Power Magnetics HF044160-2DM Capacitance 600 nF (x3) (30x) Murata GA355ER7GB473

The final boxed emi-filter volume was 183 cm3 (117 inch3) ndash a 52 reduction fromthe filter volume required for COT for SSCF1 (403 cm3246 inch3)

80


655 Drain-Source Voltage Sensing

The drain-source voltage sensing remains a critical part of the Secondary Side Fly-back concept Tab 65 lists the components and voltage reference values used forthe three sensing circuits described in Section 62 and 63 for the SSCF2 Many of thepassive component values were determined empirically

Table 65 Implemented parameters for SSCF2 drain-source voltage sensing

Component Symbol Value Package

Comparator - ADCMP600 SO-23-5MOSFET SSF IRLML0100 SO-23

Voltage Reference Uq 380 mV -Voltage Reference Uslope 180 mV -

Resistor R6 30 MΩ 1206Resistor R7 30 kΩ 0603Resistor R8 30Ω 0603Resistor R9 240Ω 0603

Capacitor C3 C5 22 pF (450 V) 1206Capacitor C4 220 pF (10 V) 0603Capacitor C6 39 pF (10 V) 0603

For the SSCF2 the same output voltage sensing circuit and parameters were re-purposed from the SSCF1 demonstrator (shown in Fig 54) For convenienceTab 66 lists the components used




81


66 SSCF2 VDS Sensing Measurements

661 Primary Side

Fig 612 shows the primary side comparator outputs in context with SSCF2 secon-dary side inductor current iL2 and primary drain source voltage VDS(S1) After theturn-ON request ends at t = 05micros VDS(S1) falls rapidly (causing Qslope to rise) toQ-ZVS threshold triggering Qqzvs and leading to S1 turn ON at asymp 25 V for a quasi-zero-voltage turn-ON The turn-ON instant can be seen where VDS(S1) suddenly dropsto 0 V from a positive valley after the ldquodouble-pulserdquo comparator signals

0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)

mdash VDS(S1)mdash Qslopemdash Qqzvsmdash iL2

Figure 612 Measured response of primary SSCF2 VDS(S1) sensing circuits

The frequency of VDS(S1) turn-OFF oscillations are high enough to trigger Qslope butthe Flyback ringing after synchronous rectification is not (indicating good dimensio-ning of R1 C1 and Uslope) A short blanking time should be included on the primarylogic after S1 turn-OFF in case oscillations exceed the Q-ZVS threshold Fig 613shows a zoom of the turn-ON request being delivered It can be seen that Qslope

naturally falls once the VDS(S1) slope begins flattening at t = 076micros

82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)


Figure 613 Zoomed view of turn-ON request with SSCF2 VDS(S1) sensing signals

662 Secondary Side

The novel application of the source-follower MOSFET to block VOUT (and highVDS(S2)) was proven to work and offer precise detection of positive S2 drain currenthelping reduce unnecessary negative current from circulating back to the input aftersynchronous rectification

Fig 614 shows a measurement of the output of the proposed synchronous rectifi-cation sensing circuit shown in Fig 64 during steady-state operation with a seriesof switching periods each with different inductor current QSR indicates positive iL2

with the rising-edge delay measured to be 70 ns and the falling edge measured tooccur consistently 45 ns before the measured zero current crossing

Fig 615 shows a zoomed plot of one such synchronous rectification period Thesmall rising edge delay will incur some additional body-diode conduction loss beforethe switch turns-ON due to the high current However the slightly premature fallingedge is especially helpful for the Secondary Side Controlled Flyback concept itprevents unwanted negative current circulating back after synchronous rectificationby allowing the controller and driver to process the signal and turn OFF S2 shortlybefore the actual zero crossing

83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)

mdash VOUTmdash QSRmdash iL2

Figure 614 SSCF2 synchronous rectification sense response for various currents

10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)


Figure 615 Zoom of measured SSCF2 synchronous rectification sense response

84

67 VOT Measurements

67 VOT Measurements

This section summarizes selected measurements of the 150 kHz VOT control takenwith the SSCF2 demonstrator using the settings listed in Tab 67 These include

bull Steady-state operation with constant output load

bull Control response to load jumps

bull Natural current limiting in overload conditions

Table 67 Implemented control settings for SSCF2 VOT operation

RMS Input Voltage 230 V 120 V

Secondary negative current ON-time TNEG 530 ns 360 nsResulting Current (VOUT = 20 V) INEG minus25 A minus17 A

Primary ON-time upper limit TUPPER 120micros 235micros


Fig 616 shows SSCF2 steady-state operation with a Q-ZVS threshold of 35 V im-plemented Such Q-ZVS turn-ON requests required secondary current of minus25 Ahalf the amplitude required for the full ZVS approach employed with the SSCF1COT demonstrator Roughly consistent peak iL2 and twait indicates energy transfermatches the load However the peak negative currents do vary slightly despite con-stant VOUT This occurs because the large Flyback ringing is of very high frequencyand not in sync with the FPGA clock ndash leading to varying S2 turn-ON voltage Thisleads to small period-to-period variations in the switching frequency since a slig-htly smaller negative current will result in slightly higher primary peak current forthe same ON-time The effect of this over an entire AC grid period can be seenin Fig 617 Despite the small variation the mean f S remains stable and close tothe 150 kHz set-point compensating the DC-link voltage ripple In summary for aconstant load adapting primary tON for fixed frequency results in stable peak iL1 iL2

and average f S throughout the entire AC period while tON and secondary twait varyin order to compensate DC-link ripple

85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)


Figure 616 Zoom of SSCF2 steady state VOT operation

0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)

mdash VDC-linkmdash iL2mdash f s

Figure 617 SSCF2 steady-state VOT operation Input 230 VRMS Output 20 V36 W

86

67 VOT Measurements

Fig 618 shows how the VOT control continuously adjusts the tON after any detectedfrequency change After the first two switching periods detected f s drifts awayfrom the 150 kHz set-point and the ON-time is trying to compensate with smalladjustments However after the third turn-ON request a sharp frequency rise from155 kHz to 174 kHz is detected In response the primary tON rapidly increases inorder to energize the primary inductance with larger iL1 and to bring f S back towardsthe 150 kHz set-point Despite the relatively large temporary deviation in switchingfrequency the quick adjustment in tON resulted in negligible deviation in outputvoltage ripple

870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)

mdash VOUTmdash f smdash iL2

Figure 618 Reaction of VOT in case of frequency deviation

672 Load Jumps

In Fig 619 the SSCF2 demonstrator undergoes an output load change from 30 to 100 load When the new high load is applied to the adapter (at around 90micros)COUT discharges faster than before and instantaneous switching frequency surgesto 227 kHz During this transient period the ON-time and peak inductor currentbegin rising to match the higher output load until the detected frequency drops backbelow the set point frequency of 150 kHz

87


After 40micros of transient the system returns to the desired frequency and averageoutput voltage as defined before ndash however the larger output ripple caused by thelarger inductor currents can be observed for the higher load A small drop in VOUT

of 590 mV can be seen during the transient due to the large sudden load change

0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)


Figure 619 VOT reaction to jump from 30 to 100 load

Fig 620 shows the behaviour during a jump from higher to lower load from 60 to 30 Primary ON-time switching frequency and secondary inductor current areplotted and the load change occurs at the time 0micros

Before the load change the peak secondary inductor current is stable at asymp15 Awhile the primary ON-time is 900 ns and switching frequency is close to 150 kHz Theload jump immediately causes a significantly larger twait while VOUT falls below thethreshold and until the subsequent turn-ON request is initiated The instantaneousswitching frequency drops to 55 kHz and the primary ON-time drops as soon as thislow frequency is detected The primary logic then adapts to the new load and after30micros the ON-time settles to around 590 ns causing peak secondary inductor currentto fall to 10 A power flow to match the reduced output load and the switchingfrequency to return back to 150 kHz

88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)

mdash tONmdash iL2mdash f s


673 Natural Current Limiting

Fig 621 shows the systemrsquos inherent overload current limiting The SSCF2 demon-strator is operating at 75 load until the time labelled 160micros when the load increasesfirst to 100 load and then beyond rated power to 110 load at time 230micros Theprimary ON-time rises until the TUPPER is reached After this VOUT drops and theoutput current hits its natural limit

Subsequently twait reduces to zero and the switching frequency stays beyondthe set-point at a maximum value dependant on the upper ON-time boundaryand output load Although the output current remains constant at the naturallimit once VOUT no longer rises above the desired threshold after primary turn-OFF the subsequent turn-ON request is generated immediately after synchronousrectification ends Fig 622 shows the transition into this zero wait time operation forthe same load change This is the equivalent scenario to that presented in Fig 513for COT control but now upper ON-time boundary TUPPER limits maximum powertransfer rather than the fixed ON-time If the load were to return to rated power orbelow the VOT control would quickly restore the rated VOUT and f S

89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)

mdash VOUTmdash f smdash iOUT

Figure 621 Measurement of natural output current limiting at 110 load

220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k

Hz)mdash f smdash iL2mdash iOUT

Figure 622 Zoomed measurement of natural output current limiting at 110 load

90

68 Efficiency Losses and Frequency Variation


681 Measurements

Efficiency was again measured using a Norma N5000 [69] Fig 623 shows measure-ments of SSCF2 compared to the 65 W COT demonstrator SSCF1 in Section 54 TheSSCF2 demonstrator shows better high-load efficiency due to

bull Lower switching frequency at high load due to VOT

bull Interleaved windings allowing a snubber-less design

bull Lossless synchronous rectification sensing

bull Reduced circulating current and loss associated with Q-ZVS turn-ON requestscompared to full ZVS requests

0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()

120 VRMS (VOT) (SSCF2)230 VRMS (VOT) (SSCF2)120 VRMS (COT) (SSCF1)230 VRMS (COT) (SSCF1)

Figure 623 Measured efficiency of demonstrator using COT and VOT controls

At low-load however despite smaller inductor currents VOT efficiency drops be-low the COT demonstrator due to higher low-load switching and turn-ON requestfrequency necessitated by the fixed frequency operation

91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding

S2 ConductionS1 Turn-OFFDiode BridgeCIN + COUT

S2 Turn-OFF + GateS1 Cond + GateS1 + S2 Turn-ON

Figure 624 Overall loss breakdown for SSCF2 with 230 VRMS input and VOT opera-tion (calculated)

The individual loss contributions were calculated using the appropriate analyticmethods referenced in [70] and are shown in Fig 624 In contrast to COT controlwhere switching frequency drops with load (see Fig 514) VOT forces switchingfrequency to remain constant causing losses associated with turn-ON requests toremain constant for all loads These include the switching gate and conductionloss due to negative current pulses and the energy circulated for Q-ZVS resultingin larger inductor currents that inflate winding core and turn-OFF loss This low-load efficiency drop is thus particularly noticeable for 230 VRMS input where peaknegative current for turn-ON requests is higher

682 Switching Frequency Variation

Lastly to assess the effectiveness of the VOT scheme it is important to check how wellit regulates the switching frequency Fig 625 is a plot of mean switching frequency(calculated over one 50 Hz grid period) versus load along with the range of primaryON-times that occurred at each load point Generally the primary ON-time moveswith the output load and for a given load the primary ON-time varies with theDC-link ripple

92


Since DC-link ripple increases with load the range of ON-times is wider at higherloads The mean switching frequency was measured to stay within 1491 kHz and1513 kHz across the load range

20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)

Max ON-timeMin ON-time

Max FreqMin FreqMean Freq

Figure 625 Minimum and maximum observed instantaneous f S and tON for SSCF2with 120 VRMS input voltage

However the range of instantaneous switching frequencies (occurring for one ortwo periods) has a wider distribution ndash plusmn6 kHz at full load to plusmn10 kHz at 10 loadDue to the nature of VOT there will always be a range of instantaneous frequenciesbecause the ON-time is corrected after any detected frequency drift However thiseffect is exacerbated

bull at low-load by the relatively large 33 ns FPGA clock period ndash 10 of theminimum tON for 230 VRMS input

bull at high-load by the varying S2 turn-ON voltages due to ringing The inductorcurrent oscillations resulting from this hard turn-ON can either compliment oroppose the build up of negative current causing non-static negative and peakinductor currents and frequency variation This varying peak negative andpositive current also negatively effects efficiency

93


69 Conclusions

Based on the conclusions from Chapter 5 this chapter aimed to improve the viabilityof the Secondary Side Controller Flyback concept by boosting converter efficiencywith a new control scheme and a modified turn-ON request approach as well asshowing system response to output load jumps To do this several novel sensingcircuits were developed and tested using an improved prototype the SSCF2

New drain-source voltage sensing circuits were developed for both S1 and S2 Theprimary side sensing approach was able to deliver fast Q-ZVS sensing successfullywhile maintaining the double pulse feature from SSCF1 to filter genuine turn-ONrequests from Flyback ringing The upgraded secondary side sensing circuit exhi-bited excellent synchronous rectification sensing reliably indicating positive draincurrent with lt 70 ns delay It also provided accurate zero current crossing detectionto avoid unwanted negative current returning to the primary side

The VOT concept was demonstrated in combination with these sensing impro-vements Various load jump measurements show the simple primary side logicrsquoscapability to autonomously match power transfer to the output load just by main-taining stable switching frequency no direct feedback is required from the outputto the primary side VOT control was shown to effectively compensate DC-linkvoltage ripple resulting in constant peak inductor currents for any given load withsmaller negative current requests As such it exhibited improved efficiency overSSCF1 of up to 899 ndash putting the Secondary Side Control Concept into the rangeof efficiency expected of 65 W Flyback adapters (see Fig 36)

Upon closer inspection however frequency stability was found to be adversely af-fected by varying S2 turn-ON voltages during Flyback ringing This combined withthe constant negative current time for turn-ON requests resulted in unnecessaryenergy circulation due to non-constant negative currents Furthermore low-loadefficiency suffered due to the fixed frequency operation and subsequent constantlosses associated with circulating energy for turn-ON requests

To help expand the capability of the the Secondary Side Controlled Flyback conceptand address the issues rising from varying S2 turn-ON voltage and poor low-loadefficiency two modifications will be investigated

bull Using a valley or level detection to only initiate turn-ON requests for lowdrain-source voltages

bull Amend the VOT control scheme to drop the switching frequency at low-loads

94

Chapter 7

Expanding the Capability of theSecondary Side Controlled Flyback

71 Chapter Outline

To explore the potential of the Secondary Side Controlled Flyback concept thischapter proposes and presents measurements of three novel upgrades to the SSCF2demonstrator from Chapter 6 Two of which address issues uncovered in previouschapters while the remaining concept introduces a new application of the SecondarySide Controlled Flyback

To address the issue of VOTrsquos poor low-load efficiency Section 72 presents a novelapplication of secondary side valley switching for the turn-ON requests reducingswitching loss and unnecessary energy circulation from turn-ON requests

Section 73 proposes a novel hybrid control scheme that combines the advanta-ges of the previous VOT and COT approaches without any additional hardwareinto a Variable Frequency Variable ON-time (VF-VOT) scheme In this VF-VOTscheme VOT is used at low loads to enforce a minimum f S while COT is used formediumhigh loads to autonomously minimize f S and maximize efficiency

Lastly for multiple output voltage compatibility Section 74 introduces a novelreverse power flow concept that with no additional hardware reverses the Flybackpower direction by using S2 to transfer energy back to the DC-link further exploitingthe unique placement of the secondary side controller

95

Chapter 7 Expanding the Capability of the Secondary Side Controlled Flyback

72 Soft Negative Current Turn-ON Requests

721 Effects of Irregular Secondary Turn-ON Voltage

As described in Section 67 the peak negative current for a turn-ON request isaffected by Flyback ringing ndash not only by the magnitude and direction of inductorcurrent at the instant of turn-ON but also by the secondary turn-ON voltage This isdue to the different stored energy dissipated from S2rsquos parasitic output capacitance atturn-ON Depending on the direction of iL2 at the instant of this hard turn-ON and themagnitude the subsequent oscillations the peak negative current will vary despiteconsistent tNEG This varying negative current subsequently leads to varying peakprimary currents and varying period-to-period switching frequency A measuredexample of this effect captured with the SSCF2 demonstrator operating with low-lineinput voltage is shown in Fig 71 A constant negative current time (tNEG) of 360 nsand constant primary tON of 219micros was used

0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)

mdash VDS(S2)mdash iL1mdash iL2

Figure 71 Measured effects of irregular S2 turn-ON voltage

Tab 71 lists the turn-ON voltages resulting inductor currents and instantaneousswitching frequencies for each of the three switching periods shown in Fig 71

96


Table 71 Inductor currents resulting from different S2 turn-ON voltages

Switching Period 1st 2nd 3rd

Secondary Turn-ON Voltage 288 V 199 V 246 V

Secondary Negative Current minus134 A minus210 A minus15 APrimary Peak Current 265 A 246 A 255 A

Secondary Peak Current 1325 A 1230 A 1275 A

Subsequent Switching Frequency 1465 kHz 1502 kHz 1480 kHz

These measurements show that relatively little turn-ON voltage deviation results insignificantly different peak inductor currents For example the first switching periodin Fig 71 yields a 40 smaller peak negative current than the subsequent perioddespite the same ON-time For high-line input voltage the effect was even morepronounced with secondary side Flyback ringing as high as 100 V This phenomenanot only affects switching frequency stability but also efficiency since tNEG has tobe chosen to work with for the worst-case turn-ON voltage ie at the peak ofFlyback ringing It follows that unnecessary negative current is circulated for lowvoltage turn-ON events increasing losses associated with turn-ON requests andenergy circulation to achieve Q-ZVS

722 Hardware

To overcome this the circuit shown in Fig 72 was added to SSCF2 to provide asignal QSOFT to indicate whether Flyback ringing is below VOUT The network actsas a level sense with USOFT representing VOUT scaled by a resistive divider

R10

R11

minus

+

minus

+

S2

QSOFT

USOFT

Figure 72 Schematic of sensing circuit for soft turn-ON requests

97


Table 72 Key components for SSCF2 soft turn-ON request sensing

Resistor R10 160 kΩResistor R11 82 kΩ

Comparator - ADCMP600DC Voltage Source USOFT 10 V

Tab 72 lists the employed component values corresponding to Fig 72 By usingthis signal along with the VOUT comparator signal QOUT (explained in section 523) ndashsuch that a turn-ON request is only initiated when both VOUT and VDS(S2) are belowdesired VOUT ndash the range of turn-ON voltages and negative current peaks is thuslimited The ldquoworst-caserdquo tNEG can then be reduced to the ON-time required for turn-ON at desired VOUT rather than at the ringing peak Decreased turn-ON voltagewill reduce S2 switching loss and the frequency deviation associated with varyingcurrent peaks However a new source of frequency instability is introduced sincea turn-ON request can now not always be initiated as soon as VOUT falls below itsreference interrupting the natural VOT rhythm

0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)


Figure 73 Measured application SSCF2 using soft S2 turn-ON requests

98


Fig 73 shows a measurement of SSCF2 after being modified with the proposedsensing circuit and turn-ON reguest logic For the first switching period QOUT fallsat t = 92micros indicating that a turn-ON request is required However VDS(S2) is abovethe VOUT threshold at this instant Instead a turn-ON request is only initiated onceQSOFT goes high indicating VDS(S2) is below VOUT threshold No such delay occursfor the second switching period because the Flyback ringing is already below VOUT

threshold when the QOUT signal goes high

723 Frequency Variation

Fig 74 compares the frequency variation of SSCF2 operating under a 150 kHz VOTcontrol scheme both with and without soft turn-ON requests employed DespiteQSOFT interrupting natural VOT rhythm and f S the overall frequency deviation issmaller than the deviation caused by varying turn-ON voltages This is due tothe competing effects of more consistent peak negative currents (reducing period-to-period frequency variation) being balanced by the interrupting effect of the softturn-ON requests The mean switching frequency with and without soft turn-ONrequests remains close to the 150 kHz set-point

20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq

Max Freq (Soft)Min Freq (Soft)

Mean FreqMean Freq (Soft)

Figure 74 SSCF2 switching frequency vs load for low-line input with and withoutsoft turn-ON requests

99


724 Efficiency

As well as reducing the switching frequency deviation the proposed soft turn-ONrequest approach also provides more consistent peak negative currents (allowing a20 reduction of tNEG) as well as reduced turn-ON switching loss for S2 As suchthe efficiency of SSCF2 was re-measured using the soft turn-ON request modifica-tion The corresponding measured efficiency is shown in Fig 75 along with SSCF2efficiency without the soft turn-ON requests

0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()

Low-Line w Soft RequestsHigh-Line w Soft Requests

Low-LineHigh-Line

Figure 75 SSCF2 VOT efficiency with and without soft turn-ON requests

The proposed technique improved efficiency by up to 15 for high-line high-loadoperation since the large S2 turn-ON voltage caused by the compounding effects oflarge Flyback ringing and full duty-cycle is removed Furthermore the largest effi-ciency improvements occurred when SSCF2 (without soft turn-ON requests) wouldnaturally turn ON S2 near the peaks of the Flyback ringing therefore more switchingloss was eliminated This phenomena was observed for high-line input at 50 60 and 78 load and is reflected in Fig 75 with small jumps in the efficiency curve Incontrast low-load turn-ON voltage is normally small since ringing amplitude fadeswith longer dead time after synchronous rectification Likewise low-line efficiencyis only marginally improved because ringing amplitude is generally smaller

100

73 VF-VOT Concept

73 VF-VOT Concept


To address the low-load efficiency deficit a novel control approach is proposed thatcombines the variable frequency (VF) property of the original COT scheme with VOTscheme to create a VF-VOT scheme The comparison of turn-ON request frequency( f R) to a reference remains from VOT but now both the reference frequency ( f REF)and primary tON are variable resulting in a subtle but important shift Rather thanmaintain constant frequency the logic infers whether power transfer is sufficient andchanges either the switching frequency (VF mode) or tON (VOT mode) dependingon whether power transfer is too high or too low While the output load determinesthe power required the power transfer for a given load tON and f S is set by VDC-linkFig 76 shows a graphical depiction of the proposal Before the primary controllerdecides whether to invoke VF or VOT operation it first determines whether instan-taneous f R is higher or lower than the current f REF to infer whether more or lesspower is needed at the output

Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER

Figure 76 Flow chart of VF-VOT control scheme

101


In the case of excessive power transfer (falling load or rising VDC-link) the controlfirst reduces the reference frequency to maintain maximum ON-time (VF mode)Once f REF reaches a pre-set lower limit (FLOWER) the control then begins reducingtON to maintain a minimum allowed switching frequency (VOT) In the case ofinsufficient power transfer (rising load or falling VDC-link) the control first increasestON transferring more energy per switching period (VOT mode) Once tON reachesthe TUPPER limit the secondary controller will naturally demand more power causingf S to rise instead (VF mode) A method of dimensioning TUPPER for rated powerat maximum desired f S without risking excessive S1 turn-OFF overshoot is givenin [81]

In summary falling power demand leads to VF mode and rising power demandleads to VOT mode and once either of the respective lower and upper boundariesare reached vice-versa The VF-VOT approach ensures that the Flyback is alwaysoperating at the minimum possible switching frequency capable of supporting theoutput load ndash universally reducing the loss and circulating energy associated withswitching frequency and turn-ON requests (compared to VOT control) Both tON

and f REF operate under two parallel standard PI control structures similar to thatshown in Fig 68 [82]

732 Hardware and Control Set-Up

To make a direct efficiency comparison the SSCF2 demonstrator was used withoutany hardware changes From SSCF2rsquos hardware parameters VF-VOTrsquos upper tON

limit (TUPPER) was chosen to give a maximum f S of 150 kHz with an FLOWER of 90 kHzchosen to give an equal share of VF and VOT action across the load range A tON

lower limit (TLOWER) was required to avoid negligiblezero power transfer that mightdisturb the PI control loop Tab 73 lists the VF-VOT control boundaries employedon SSCF2

Table 73 Implemented control limits for VF-VOT with SSCF2

Maximum ON-time (High-Line) TUPPER 125microsMaximum ON-time (Low-Line) TUPPER 245micros

Minimum ON-time TLOWER 021microsMinimum Switching Frequency FLOWER 90 kHz

102

73 VF-VOT Concept

733 Measured Switching Frequency and ON-time Behaviour

Taken from the SSCF2 demonstrator Figs 77- 79 show measurements of f S andtON with respect to DC-link ripple for a range of loads Fig 77 shows this for 90 load where f S drifts naturally with DC-link ripple However f S never falls to FLOWER

meaning tON is never changed from TUPPER This COTVF action allows the converterto operate with the lowest f S possible with the instantaneous VDC-link autonomouslyreducing energy circulation from turn-ON requests and switching and gate loss to aminimum

0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)

ndash VDC-linkndash tONndash f S

Figure 77 SSCF2 low-line VF-VOT at 90 load

In contrast Fig 78 shows 60 load where both VF and VOT work together tocompensate DC-link ripple As soon as the increasing VDC-link causes TUPPER topush f S down to FLOWER tON is reduced This VOT action then maintains FLOWER

until VDC-link is low enough that TUPPER cannot support the load whereby f S is thenincreased The noise present in tON during rising f S is due to the f R estimated by thecontroller not matching real f S

103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept

Fig 79 shows the VF-VOT behaviour during 25 load wherein the required powerand DC-link ripple are low enough that tON never rises to TUPPER and the converterstays in VOT mode to maintain FLOWER preventing f S falling outside of desiredlower limit This thus represents the largest loss associated with turn-ON requestsdue to the ldquoartificiallyrdquo high switching frequency

As in Chapter 6 the 65 W SSCF2 demonstrator was operated at several load pointsbetween 10 and 100 load Measurements of f S and primary tON were taken at theextremities of the DC-link ripple at each corresponding load point and are shownin Fig 710

20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S

Figure 710 SSCF2 VF-VOT Switching frequency and primary ON-time vs load

As predicted at low-loads the VOT action holds f S at the minimum 90 kHz whileat high-loads the VF action maintains maximum ON-time ensuring the minimumswitching frequency possible with the instantaneous DC-link voltage Between 30 and 70 load both VF and VOT actions work together to both ensure minimumpossible switching frequency depending on DC-link ripple and simultaneouslyensure that FLOWER is not breeched With a lower FLOWER limit the point at whichVOT takes over would occur at a lower load

105


734 Efficiency

The measured efficiencies of SSCF2 demonstrator utilising both VF-VOT and VOTcontrol schemes are plotted in Fig 711 both with the soft-turn-ON-request techni-que applied For comparison the efficiency of the professional PMP9208 is alsoplotted High-load efficiency matches that achieved with VOT indicating that anyloss reduction due to lower f S is immediately cancelled by the higher constant peakcurrents

0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()

Low-line (VF-VOT)High-line (VF-VOT)Low-line (PMP9208)High-line (PMP9208)

Low-line (VOT 150kHz)High-line (VOT 150kHz)

Figure 711 Comparison of SSCF2 VF-VOT vs 65 W TI PMP9208 demonstrator

Low-load efficiency is significantly improved due to the reduced loss associated withf S and turn-ON requests The best efficiency (9077 ) was achieved at high-loadwith high-line input almost identical to VOT However high-line efficiency has asteeper drop at low-load than low-line after entering full VOT control due to thelarger negative current required for turn-ON requests As shown in Fig 710 thedemonstrator enters full VOT mode below asymp 40 load once the FLOWER limit is hitThis behaviour is reflected in Fig 711 whereupon the efficiency for both high- andlow-line begins to rapidly decrease In practice FLOWER could be reduced beyond90 kHz to continue boosting low-load efficiency

106

73 VF-VOT Concept

The TI PMP9208 uses a rival opto-isolator-less control (primary side regulation)but uses the same core shape and turns-ratio The PMP9208 uses a passive diodepair for secondary synchronous rectification whereas the Secondary Side ControlledFlyback uses an active switch S2 and therefore exhibits superior efficiency at high-load where secondary side currents are high However the primary side regulationconcept requires no additional negative current and energy circulation for turn-ONrequests and as such boasts superior low-load efficiency

In summary the Secondary Side Controlled Flyback concept in combination withVF-VOT control achieved good high-load efficiency out-performing the PMP9208with a peak of 9077 However a minimum switching frequency of 90 kHz wasinsufficient to push low-load efficiency in-line with that of the PMP9208 but wassignificantly better than 150 kHz VOT control Low-load loss remains a disadvantageof the Secondary Side Controlled Flyback concept By re-measuring SSCF2 efficiencywith the VOT control (described in Section 64) set at different reference frequencies(FREF) it is possible to see how lowering FLOWER in VF-VOT control would increaselow-load efficiency (shown in Fig 712) It is unknown how EMI-filter design mightconstrain how far FLOWER could be reduced realistically

0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()

150 kHz135 kHz120 kHz105 kHz90 kHz75 kHz60 kHz

Falling FREF

Figure 712 Measured low-line SSCF2 VOT efficiency with various FREF Replicatingthe effect of reducing FLOWER in VF-VOT control

107


74 Reverse Power Flow for Multiple Output Voltages

Key advantages of the Secondary Side Controlled Flyback concept include the di-rect access to VOUT synchronous rectification switch S2 and to any load disconnectswitch [58] Combining these features offers a novel opportunity for reverse po-wer flow for discharging COUT back to CDC-link in a non-dissipative way withoutany additional components or signal coupling useful for multiple output voltageapplications such as USB-PD [45]

This section explores discharging COUT from 20 V to 5 V [83] Such a change willcause an inconsequential rise in the DC-link voltage as the energy stored in COUT istypically much smaller than that of CDC-link due to the voltage difference

Currently the most common existing strategy for discharging the output capacitor(COUT) is by using an additional switch and resistor in parallel with COUT [84 85]In contrast the proposed solution requires no such additional hardware and takesadvantage of the secondary side controllerrsquos direct access to VOUT and S2 by simplyreversing the Flyback direction using S2 to transfer energy back to the DC-linkturning S1 into the synchronous the rectifications switch


Reverse power flow is achieved by turning OFF the load-disconnect switch andrepeatedly switching S2 with period tNEG(R) to energize the coupled inductor withnegative current pulses resulting in primary side current (iL1) via S1 body diodeand net energy transfer from secondary to primary side However any currentthrough S1 body diode will discharge COSS(S1) and register as a turn-ON requeston the independent primary side controller and S1 will turn-ON This will riskpositive iL1 and energy returning to the output nullifying any reverse power flowTo avoid this the secondary controller can take advantage of the primary controllerrsquossimplicity by

bull Sending negative current pulses below the primary controllerrsquos lower fre-quency limit at a fixed low frequency (FRPF) ndash tricking the VOT VF-VOT controlinto reducing the primary ON-time to its minimum value (TLOWER)

bull Sending large negative current pulses such that S1 turns ON for TLOWER andthen OFF again all while iL1 is negative avoiding unnecessary positive iL1

108


This approach requires no additional primary side logic complexity the primarycontroller will not even be aware that reverse power flow is occurring Thus thesecondary controller can simply resume steady-state operation with normal turn-ON requests once VOUT has fallen to the new desired value

742 Secondary Side VOT for Safe Reverse Power Flow

Negative currents should be large enough to encompass the entire primary TLOWER athigh and low VOUT However using a constant tNEG(R) capable of achieving sufficientcurrent at low VOUT may yield overly large negative currents at higher VOUT andresult in a turn-OFF overshoot that breaches S2rsquos breakdown voltage ThereforetNEG(R) must be slowly increased as VOUT falls

To avoid adding any active VOUT measurement the soft turn-ON request voltagesensing proposed in Section 722 can be re-purposed along with the VOT conceptdiscussion in Section 641 for safe variable ON-time reverse-power flow with noadditional hardware Fig 713 shows an exaggerated sketch of various waveformsfor the proposed concept

As described while VOUT is decreasing FRPF (1TRPF) remains constant To com-pensate falling VOUT tNEG(R) can be seen to sporadically increase pushing the peaknegative secondary inductor current (iL2) To detect when tNEG(R) should be modifiedthe secondary side controller infers VOUT using the existing comparator signal QSOFTThe signal QSOFT indicates whether secondary drain-source voltage (VDS(S2)) is aboveor below VOUT More specifically

1 After S2 turn-OFF VDS(S2) necessarily rises above the VOUT threshold due toreflected DC-link voltage This toggles the comparator output QSOFT to go low

2 QSOFT stays low until the iL1 reduces to zero ndash VDS(S2) no longer reflects VDC-link

and thus VDS(S2) falls back below VOUT threshold toggling QSOFT back to high

3 Therefore the time that QSOFT is low (tiL1) ndash represents the size of the negativecurrent pulse If this time decreases it implies that VOUT has fallen

4 The tiL1 measured after the very first pulse can be used as a reference (TiL1(REF))If tiL1 falls below this reference tNEG(R) increases until tiL1 again matches TiL1(REF)

109


This novel approach of adapting the VOT scheme to the secondary side thus requiresno additional sensing hardware It ensures consistent peak negative currents largeenough to consume the minimum primary ON-time for the entire VOUT range andavoids excessive S2 turn-OFF overshoot while guaranteeing net reverse power flow

gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT

TimetNEG(R) tNEG(R)+

tNEG(R)++

20 V VOUTthreshold

TRPF TRPF TRPF TRPF TRPF

tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1

Figure 713 Sketch of reverse power flow concept

110


743 Constraints on Minimum Negative Current Time

To ensure that negative iL1 always encompasses the entire primary ON-time a lowerlimit for tNEG(R) is needed This lower limit can be expressed as

tNEG(R) gtN L2 VDC-link

L1 VOUTTLOWER (71)

Additionally initial implementation of the proposed concept on the SSCF2 alsorevealed that a minimum energy must be delivered in each switching period andmust be larger than the energy needed to re-charge COSS(S1) after L1 has de-energizedOtherwise the primary side will return more energy back to the output while re-charging COSS(S1) than is delivered back to CDC-link in the first place Fig 714 showsa measurement of such a scenario

0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)


Figure 714 Circulating energy due to COSS(S1)

The negative iL1 is large enough to encompass the primary TLOWER but iL1 continuesto rise while COSS(S1) charges Subsequently the peak positive current is larger thanthe peak negative current resulting in net positive power flow from CDC-link toCOUT This current flow into COSS(S1) (which is especially large for super-junctionMOSFETs [86]) will always cause some circulation of energy back to COUT even if S1

turns OFF during negative current

111


To ensure net power flow from COUT to CDC-link tNEG(R) must always yield a negativecurrent large enough to encompass the primary TLOWER (71) and simultaneouslyreturn more energy than required to recharge COSS(S1) This relation is given in (72)where QCOSS(S1) represents the charge required to bring COSS(S1) from 0 V to VDC-link

tNEG(R) gt1

VOUT

radic2 L2 VDC-link QCOSS(S1) (72)

To satisfy (71) and (72) during reverse power flow tNEG(R) must rise as VOUT fallsfurther justifying the proposed addition of VOT to the novel reverse power flowconcept Although satisfying both minimum tNEG(R) constraints and ensuring safeS2 turn-OFF overshoot may leave a narrow allowable range for tNEG(R) only a singleworkable value for tNEG(R) is required for any given VOUT

744 Measurements

The concept was tested using the SSCF2 demonstrator with VF-VOT primary controland 120 VRMS input The exact ldquohandshakerdquo used to indicate a required change inVOUT is standardized in USB-PD and not discussed here but information can befound in [46] Instead the secondary controller was programmed to supply 20 Vand after an arbitrary dead time initiate reverse power flow to discharge to 5 Vbefore continuing steady state operation

Table 74 Settings used for reverse power flow and subsequent voltagescurrents

Fixed Discharge Switching Frequency FRPF 65 kHzInitial tNEG(R) (VOUT = 20 V) tNEG(0) 930 ns

Min VF-VOT Switching Frequency FLOWER 90 kHzMin VF-VOT ON-time TLOWER 300 ns

Desired Negative iL2 IL2(RPF) minus450 AReturned Peak iL2 due to COSS(S1) IL2(POS) 375 AResulting Peak VDS(S2) Overshoot VDS(S2) 84 V

Fig 715 shows a measurement of the entire reverse power flow procedure Theconverter is initially supporting a 20 V 30 W load using the VF-VOT control schemeuntil t = 4 ms at which point the artificial ldquohandshakerdquo occurs and the load-disconnectswitch is turned OFF

112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V

)mdash VOUTmdash iL2

Figure 715 Measurement of reverse power flow discharging 20 V to 5 V

The secondary controller then waits for a relatively long time (4 ms) to both ensurethat drain-source voltages and inductor currents stabilize before starting reversepower flow and to force the primary ON-time down to its lower limit TLOWER Theproposed VOT reverse power flow approach then begins and successfully maintainsconstant peak negative currents while VOUT falls

At t = 75 ms the desired VOUT has been achieved at which point the load-disconnect switch is turned back ON and steady state operation resumes to supportthe new 5 V load As indicated by the desired and returned currents listed in Tab 74approximately 69 of the energy delivered in the negative current pulse is returnedafter charging COSS(S1) Consequently the discharge takes a relatively long time ofasymp 70 ms However in the context of consumer USB-PD adapters undergoing occa-sional load change this is a short enough discharge time that would not be noticedby an end-user Using a primary device with a smaller COSS would result in fasterreverse power flow

This shows the Secondary Side Controlled Flyback converterrsquos capability to dis-charge its own output capacitor in a non-dissipative manner without any additionalprimary side complexity

113


75 Conclusion

This chapter presented three methods of expanding the capability of the SecondarySide Controlled Flyback converter a novel soft turn-ON request concept a newhybrid VF-VOT control scheme and a novel reverse power flow concept for multipleoutput voltage capability

Firstly to address two main conclusions of Chapter 6 two novel concepts wereproposed soft-turn-ON-requests and Variable Frequency Variable ON-time controlThe soft turn-ON requests resulted in a 11 efficiency improvement at high-linehigh-load due to reduced switching loss and reduced loss associated with unneces-sary energy circulation from turn-ON requests However frequency stability onlyslightly improved since the soft turn-ON requests now can not always be initiatedwhen required but only when Flyback ringing and output voltage are simultane-ously below their respective thresholds interrupting natural VOT rhythm

The new control scheme combined two existing control approaches (constantON-time and variable ON-time) to make a variable frequency variable ON-timecontrol (VF-VOT) This scheme allowed the Flyback switching frequency to drift atmedium-high loads to maximize efficiency and to vary primary ON-time at lowloads to maintain a minimum switching frequency Although low-load efficiencystill dropped once VOT became dominant this scheme resulted in an efficiency boostacross most of the load range putting the Secondary Side Flyback efficiency in linewith existing Flyback demonstrators such as the TI-PMP9208

Lastly reverse power flow was demonstrated using a novel concept whereby theoutput capacitor (COUT) is discharged back to the input capacitor in a non-dissipativemanner without any added complexity to the primary side logic While successfulseveral constraints on the negative currents used to discharge COUT were discoveredthat limit the speed of the overall discharge process These constraints include thebreakdown voltage of S2 limiting the maximum negative current and the parasiticoutput capacitance of S1 limiting the minimum workable negative current Forcompatibility with USB-PD applications an output voltage discharge from 20 V to5 V was demonstrated and took 70 ms

114

Chapter 8

Conclusions

81 Summary

This thesis presented an investigation of a novel power adapter concept the Se-condary Side Controlled Flyback converter by means of sub-circuit design controlscheme conceptualization prototyping and measurement analysis The overall re-search objective was as follows


The target application explored in this thesis was a 65 W universal adapter providing20 VDC output from either 120 VRMS or 230 VRMS To achieve the above objective withinthis context the author focused on four diverse yet interrelated sub-objectives whenconsidering the feasibility viability and capability of the Secondary Side ControlledFlyback converter concept





115

Chapter 8 Conclusions

811 Feasibility

The general feasibility of the secondary side controlled Flyback concept was provenin hardware using a 65 W demonstrator the SSCF1 The main controller was basedon the secondary side of the coupled inductor and was entirely isolated from thegrid input voltage All ldquocommunicationrdquo between primary and secondary sidesoccurred without any auxiliary isolated signal coupling but instead using a noveldrain-source voltage sensing circuit across the primary side switch to reliably detecta so-called ldquoturn-ON requestrdquo transmitted from the secondary side via the Flybackrsquoscoupled inductor A working start-up routine was presented and the demonstratorwas shown to sustain a stable output voltage across the load range

To show this feasibility the primary side switch was supplemented with a sim-ple yet novel drain-source voltage sensing circuit that allowed the primary side toautonomously filter out unwanted zero voltage crossings leading to reliably safeturn-ON of the primary switch that was as fast as existing opto-isolator alternativesmaking the concept competitive with existing secondary side control concepts butrequiring no additional isolated signal coupling components

To test the limits of the conceptrsquos feasibility constant primary ON-time was usedfor maximum secondary side control However the price of complete secondaryside control with constant primary ON-time is that the switching frequency variesconsiderably with both output load and DC-link ripple This in combination withthe large negative current required for full zero voltage turn-ON requests resultedin poor efficiency peaking at 8490 (below that expected of 65 W Flyback adap-ters) The secondary side synchronous rectification sensing also exhibited slow zerocurrent crossing response leading to unwanted negative current every switchingperiod further reducing efficiency especially at high loadhigh switching frequency

812 Viability

To improve the viability of the concept as an alternative to existing solutions theefficiency had to be improved In particular the losses caused by the large negativecurrent for turn-ON requests in combination with the large switching frequencyrange resulting from the constant ON-time control had to be reduced An improved65 W prototype (the SSCF2) included primary drain-source voltage sensing for quasi-zero-voltage turn-ON requests and improved synchronous rectification sensing Itwas optimised for a new control scheme (variable ON-time) for operation with

116

81 Summary

constant 150 kHz switching frequency The demonstrator and control scheme werethen exposed to several load jumps to ensure viability in non ideal load conditions

The quasi-zero-voltage (Q-ZVS) based turn-ON commands required significantlyreduced negative current pulses from the secondary side freeing more of the duty-cycle for power transfer and reducing circulating currents The variable ON-timecontrol resulted in a split controller structure whereby secondary side controller stillregulated the output voltage with turn-ON requests but the primary side regulatedthe switching frequency with variable ON-time This was shown to automaticallymatch power transfer to the output load and compensate DC-link ripple to ensureconstant peak inductor currents for a given load With SSCF2rsquos improved coupledinductor the combination of the Q-ZVS turn-ON requests with constant switchingfrequency led to improved efficiency across the load range peaking at 8990 Thisis within the expected efficiency range for bespoke 65 W Flyback adapters

While this approach required additional primary side complexity the improvedviability is significant optimal coupled inductor design smaller peak inductor cur-rents improved efficiency and reduced EMI-filter while maintaining all key featuresof the proposed concept (direct output voltage access without isolated signal cou-pling) The main weaknesses of the approach were poor low-load efficiency due tothe fixed switching frequency and varying turn-ON voltages due to natural Flybackringing that caused varying negative currents and varying switching frequency of plusmn10 kHz (along with oversized negative current for turn-ON requests)

813 Capability

To explore the capability of the Secondary Side Controlled Flyback concept threeadditional novel concepts were shown to push the efficiency and exploit the uniquepossibilities of a secondary side based controller with active synchronous rectifica-tion switch These concepts were tested using the SSCF2 demonstrator

To address the non-consistent negative currents caused by varying turn-ON re-quest turn-ON voltage a level detection circuit was appended to the secondary sideswitchrsquos drain that ensured turn-ON requests were only initiated for low drain-source voltages so-called soft turn-ON requests This was shown to both reduceswitching loss and the variation of negative current peaks This allowed the turn-ONrequest time to be reduced to decrease unnecessary circulating current and boostefficiency by up to 15 at high-line high load However the soft-turn-ON requestsnecessarily interrupt the natural rhythm of the constant frequency control and thus

117


switching frequency variation was only slightly reducedTo truly boost the efficiency capability of the Secondary Side Controlled Flyback

a hybrid control scheme was developed In short the primary side maintainedconstant ON-time to allow the switching frequency to naturally drift with DC-linkripple and load unless switching frequency dropped to or beyond a lower limit atwhich point the ON-time became variable to ensure constant switching frequency atthis lower limit This removed the loss associated with constant switching frequencyfor medium to high loads while avoiding very low switching frequencies at lowloads Combining this control with the soft turn-ON requests using SSCF2 exhibitedimproved efficiency across the load range with a peak of 9077

A new capability of reversing the power flow of the Flyback using the secondaryswitch (in order to reduce the output voltage in a non-dissipative manner) wasdemonstrated for compatibility with 20 V to 5 V output voltage change Without anyadditional primary side complexity it was shown that by sending large negativecurrent pulses from the secondary side the primary side can operate as normalwithout even being aware that reverse power flow is taking place This allows thereverse power flow and multiple output voltage compatibility to be added withoutadding any primary side complexity

This showed the Secondary Side Controller Flyback converter to be capable of anefficiency rivalling that of competitor control strategies while offering direct outputvoltage access without any isolated signal coupling along with multiple outputvoltage compatibility via reverse power flow

82 Outlook Short Term Further Work

Important further work identified by the author includes the following issues

bull A comparison of EMI-filter requirements for VOT and VF-VOT controls

ndash VF-VOT has a broader frequency range than VOT but the peak currentsare smaller when the switching frequency is at the lower limit Is there atrade-off between low load efficiency and EMI-filter requirements

bull Repsonse to output load short circuit failure

ndash How can the secondary side sense the failure and safely shut down

ndash How can the primary side infer the shut-down and re-initiate start-up

118

83 Outlook Wide Band Gap Devices


A large amount of power-electronics research today is focussed on the developmentof gallium-nitride (GaN) and silicon-carbide (SiC) based switching devices Forthe same chip area the advantages of these materials over silicon stem from thehigher energy band-gap between the valence and conduction bands (giving higherblocking voltages) and higher electron mobility (giving lower ON-state resistance(RDS(ON))) Furthermore the parasitic output capacitance of a wide-band-gap deviceis smaller than that of a comparable silicon device [87] SiC MOSFETs show potentialfor market application in high voltage applications (several kilo-volts) while GaNdevices are often in competition with super-junction MOSFETs in the 600 V blockingvoltage range [88] As such there are plenty of examples of very high-efficiencyFlyback demonstrators using GaN devices [89] Two potential benefits of usinga GaN High Electron Mobility Transistor (HEMT) device in the Secondary SideControlled Flyback concept are introduced here as suggested areas of further work

831 Turn-ON Request Loss

The efficiency of the Secondary Side Controlled Flyback converter may benefit froma GaN based S1 Not only because of the improved RDS(ON) but also due to thereduced negative current required to achieve a turn-ON request This may allowthe Flyback to be pushed into very high frequencies for high power density whilemaintaining the competitive efficiency proven to be possible in this thesis

832 Reverse Power Flow

Reverse power flow whereby COUT is discharged with short pulses with ON-timetNEG(R) was shown in Section 74 with a super-junction MOSFET for S1 The processwas slowed by the energy circulation caused by the charging and discharging ofS1rsquos large parasitic output capacitance (COSS(S1)) The proposed reverse power flowapproach in Section 742 maintained constant peak negative current at switchingfrequency FRPF As such it is possible to speculate how reverse-power-flow dischargetime (tDIS) would change with the ratio of ENEG(R) (energy removed from COUT duringtNEG(R)) to EPOS(R) (the energy returned to COUT due to the re-charging of COSS(S1))Replacing S1 with an equivalent 600 V e-mode GaN HEMT might allow much shortertDIS due to the smaller COSS and the smaller x that would result

119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF

ECOUT |20V minus ECOUT |5V

ENEG(R)(1 minus x)(82)

Fig 81 shows expected tDIS for varying x using (82) assuming the same FRPF andtNEG(R) given in Tab 74 The x value for the super-junction device used for SSCF2(IPL60R125C7) was calculated using peak currents given in Tab 74 The correspon-ding tDIS given by (82) matches the measured value in Section 744 (70 ms)

0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS

(ms) CoolMOS C7 125 mΩ (IPL60R125C7)

e-mode GaN 52 mΩ

Figure 81 Estimated reverse power flow discharge time for versus ratio x

By using the parameter CO(tr) (an approximation of a devicersquos effective COSS) thetheoretical tDIS for other devices can be estimated by comparing their CO(tr) to thatof the device used in SSCF2 and then inferring the time necessary to re-charge thenew CO(tr) to find the resulting peak currents to re-calculate x With this method anestimate for the tDIS of an e-mode GaN HEMT has been added to Fig 81 Althoughany parasitic effects of the coupled inductor have not been considered here Fig 81indicates that the e-mode GaN HEMT device has an x of 4 and thus tDIS could bearound seventeen times faster despite using the same FRPF and tNEG(R)

120

Abbreviations and Symbols

Abbreviations

Abbreviation Definition

COT Constant-ON-timeVOT Variable-ON-time

VF-VOT Variable-Frequency Variable ON-timeSSCF Secondary Side Controlled FlybackSMPS Switched Mode Power SupplyZVS Zero-voltage-switching

Q-ZVS Quasi-zero-voltage-switchingCM Common modeDM Differential modeRPF Reverse Power FlowEMI Electromagnetic interference

MOSFET Metal oxide semiconductor field effect transistorFPGA Field-programmable gate arrayGaN Gallium NitrideSiC Silicon CarbideIC Integrated Circuit

PCB Printed Circuit Board

Pri PrimarySec Secondary

Sync Rec Synchronous RectificationCap Capacitor

121


Symbols

Component Parameter

Symbol Unit Description

CDC-link F Primary side capacitance

CIN F Alternative (more general) term for CDC-link

COUT F Secondary side capacitance

COSS F Parasitic output capacitance

COSS(S1) F Primary side switch parasitic output capacitance

CO(tr) F Effective parasitic output capacitance

CSn F RCD snubber capacitance

C1 F Capacitor for VDS(S1) sensing


C3 F Capacitor for VDS(S1) Q-ZVS sensing




DSn - RCD snubber diode

D0 - Synchronous rectifier diode

D1 - Diode for VDS(S1) sensing


D3 - Zener Diode for VDS(S1) sensing

D4 - Diode for VDS(S2) sensing circuit


ECOUT J Energy stored in output capacitance COUT

ENEG(R) J Energy from reverse power flow pulse

EPOS(R) J Energy returned after reverse power flow pulse

FLOWER Hz Lower switching frequency limit

f R Hz Instantaneous request switching frequency

f REF Hz Reference switching frequency (variable)

FREF Hz Reference switching frequency (constant)

FRPF Hz Reverse power flow switching frequency

f S Hz Switching frequency

f S(max) Hz Maximum switching frequency

id A Drain current

122


iL1 A Primary side inductor current

iL2 A Secondary side inductor current

IL2(NEG) A Negative current from reverse power flow pulse

IL2(POS) A Positive current after reverse power flow pulse

INEG A Negative current for turn-ON request

iOUT A Output current

k - Coupling factor between L1 and L2

L1 H Primary side inductance

L2 H Secondary side inductance

N - Turns-ratio of N1 to N2

N1 - Number of primary side windings

N2 - Number of secondary side windings

PIN W Input power

Ploss W Power loss

Pneg W Power consumed by turn-ON requests

Prated W Rated output power

QCOSS C Parasitic output charge

QOUT V Output voltage sensing comparator

QPRI V Primary side VDS sensing comparator

Qqzvs V VDS(S1) sensing comparator for Q-ZVS

Qslope V Comparator for VDS(S1) slope detection

QSOFT V Comparator for soft turn-ON requests

QSR V VDS(S2) sensing comparator

RSn Ω RCD snubber resistance

R1 Ω Resistor for VDS(S1) sensing


R3 Ω Resistor for VDS(S2) sensing circuit

R4 Ω Resistor for VOUT sensing circuit


R6 Ω Resistor for VDS(S1) Q-ZVS sensing


R8 Ω Resistor for VDS(S1) slope sensing


R10 Ω Resistor for soft turn-ON request sensing


123


SSF - Source follower MOSFET

S1 - Primary side Flyback switch

S2 - Secondary side Flyback switch

Tdesired s Desired switching period

tDIS s Total reverse power flow discharge time

tiL1 s Time of positive iL1 after reverse power flow pulse

TiL1(REF) s Reference tiL1 set by initial tiL1

TLOWER s Lower ON-time limit

TNEG s Negative current ON-time for turn-ON request

tNEG(R) s ON-time for reverse power flow discharge pulses

tON s Variable ON-time for VOT amp VF-VOT

TON s Constant ON-time for COT

TRPF s Reverse power flow switching period

TS s Switching period (constant)

tS s Switching period (variable)

TUPPER s Upper ON-time limit

twait s Time between sync rec and turn-ON request

Ugrid V AC input voltage source

UREF V Reference voltage for VOUT comparator circuit

USF V Gate voltage supply for SSF

Uslope V Reference voltage for VDS(S1) slope sensing

USOFT V Reference voltage for soft turn-ON requests

Uq V Reference voltage for Q-ZVS VDS(S1) sensing

U1 V Reference voltage for VDS(S1) sensing

VDC-link V Voltage across DC-link capacitor CDC-link

VDC-link(min) V Minimum expected VDC-link

VDC-link(min) V Maximum expected VDC-link

VDS V Drain-source voltage

VDS(S1) V Primary switch drain-source voltage

VDS(S2) V Secondary switch drain-source voltage

VGS V Gate-source voltage

VGS(th) V Gate-source threshold voltage

VIN V Input voltage from UGRID

VOUT V Output voltage

Vrated V Rated output voltage

x - Ratio of ENEG(R) to EPOS(R)

124

Bibliography

[1] P T Krein Elements of Power Electronics Second Edition New York New YorkOxford University Press 2015

[2] N Mohan T M Underland and W P Robbins Power Electronics ConvertersApplications and Design Hoboken New Jersey John Wiley amp Sons Inc 2003

[3] F Udrea and G Deboy and T Fujihira ldquoSuperjunction Power Devices HistoryDevelopment and Future Prospectsrdquo IEEE Transactions on Electron Devicesvol 64 no 3 pp 720ndash734 March 2017 issn 0018-9383 doi 101109TED20172658344

[4] S Chen and D Xiang and H Wang and K Tabira and Y Niimura ldquoAdvantageof super junction MOSFET for power supply applicationrdquo in 2014 InternationalPower Electronics and Application Conference and Exposition November 2014pp 1388ndash1392 doi 101109PEAC20147038067

[5] M K Kazimierczuk Pulse Width Modulated DCminusDC Power Converters SecondEdition Hoboken New Jersey John Wiley amp Sons Inc 2015

[6] R E Tarter Principles of Solid-State Power Conversion Indianapolis IndianaHoward W Sams amp Co Inc 1985

[7] Wuerth Elektronik Switch Mode Power Supply Topologies Compared httpshttpwwwwe- onlinecomwebenpassive_components_custom_

magneticsblog_pbcmblog_detail_electronics_in_action_45887phpAccessed January 2018

[8] K Billings and T Morey Switchmode Power Supply Handbook Third EditionNew York New York The McGraw-Hill Companies Inc 2011

[9] T T Vu and S OrsquoDriscoll and J V Ringwood ldquoPrimary-side sensing for aflyback converter in both continuous and discontinuous conduction moderdquoin IET Irish Signals and Systems Conference (ISSC 2012) June 2012 pp 1ndash6 doi101049ic20120195

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BIBLIOGRAPHY

[10] Laszlo Huber and Milan M Jovanovic ldquoEvaluation of Flyback Topologies forNotebook ACDC AdpaterCharger Applicationsrdquo in HFPC Conference Procee-dings May 1995

[11] T Halder ldquoStudy of rectifier diode loss model of the Flyback converterrdquo in 2012IEEE International Conference on Power Electronics Drives and Energy Systems(PEDES) December 2012 pp 1ndash6 doi 101109PEDES20126484492

[12] M T Zhang M M Jovanovic and F C Y Lee ldquoDesign considerations andperformance evaluations of synchronous rectification in flyback convertersrdquoIEEE Transactions on Power Electronics vol 13 no 3 pp 538ndash546 May 1998issn 0885-8993 doi 10110963668117

[13] T Halder ldquoPower density thermal limits of the flyback SMPSrdquo in 2016 IEEEFirst International Conference on Control Measurement and Instrumentation (CMI)January 2016 pp 1ndash5 doi 101109CMI20167413699

[14] Chih-Sheng Liao and K M Smedley ldquoDesign of high efficiency Flyback con-verter with energy regenerative snubberrdquo in 2008 Twenty-Third Annual IEEEApplied Power Electronics Conference and Exposition February 2008 pp 796ndash800doi 101109APEC20084522812

[15] M Mohammadi and M Ordonez ldquoFlyback lossless passive snubberrdquo in2015 IEEE Energy Conversion Congress and Exposition (ECCE) September 2015pp 5896ndash5901 doi 101109ECCE20157310487

[16] R L Ozenbaugh and T M Pullen EMI Filter Design Third Edition New YorkNew York Marcel Dekker Inc 2001

[17] D Miller and M Reddig and R Kennel ldquoNovel EMI line filter system forSMPSrdquo in 2014 IEEE Fourth International Conference on Consumer ElectronicsBerlin (ICCE-Berlin) September 2014 pp 272ndash276doi 101109ICCE-Berlin20147034329

[18] L Xue and J Zhang ldquoHighly Efficient Secondary-Resonant Active ClampFlyback Converterrdquo IEEE Transactions on Industrial Electronics vol 65 no 2pp 1235ndash1243 February 2018 issn 0278-0046 doi 10 1109 TIE 2017 2733451

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[19] A Letellier and M R Dubois and J P Trovao and H Maher ldquoGallium Ni-tride Semiconductors in Power Electronics for Electric Vehicles Advantagesand Challengesrdquo in 2015 IEEE Vehicle Power and Propulsion Conference (VPPC)October 2015 pp 1ndash6 doi 101109VPPC20157352955

[20] J Lutz Semiconductor Power Devices Heidelberg Springer 2011

[21] G Deboy and N Marz and J P Stengl and H Strack and J Tihanyi and HWeber ldquoA new generation of high voltage MOSFETs breaks the limit line ofsiliconrdquo in International Electron Devices Meeting 1998 Technical Digest (CatNo98CH36217) December 1998 pp 683ndash685 doi 10 1109 IEDM 1998 746448

[22] D Schroefer Leistungselektronische Bauelemente Heidelberg Springer 2006

[23] W Konrad A high efficiency modular wide input voltage range power supply (PhDThesis) Graz Austria Graz University of Technology 2015

[24] Infineon Technologies IPL60R125C7 600V CoolMOS C7 Power TransistorhttpswwwinfineoncomdgdlInfineon-IPL60R125C7-DS-v02_01-ENpdfAccessed January 2018

[25] R Erickson M Madigan and S Singer ldquoDesign of a simple high-power-factor rectifier based on the flyback converterrdquo in Fifth Annual Proceedings onApplied Power Electronics Conference and Exposition March 1990 pp 792ndash801doi 101109APEC199066382

[26] K H Liu and F C Y Lee ldquoZero-voltage switching technique in DCDC con-vertersrdquo IEEE Transactions on Power Electronics vol 5 no 3 pp 293ndash304 July1990 issn 0885-8993 doi 1011096356520

[27] H Dong and X Xie and K Peng and J Li and C Zhao ldquoA variable-frequencyone-cycle control for BCM flyback converter to achieve unit power factorrdquo inIECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics SocietyOctober 2014 pp 1161ndash1166 doi 101109IECON20147048649

[28] J Park Y S Roh Y J Moon and C Yoo ldquoA CCMDCM Dual-Mode Synchro-nous Rectification Controller for a High-Efficiency Flyback Converterrdquo IEEETransactions on Power Electronics vol 29 no 2 pp 768ndash774 February 2014issn 0885-8993 doi 101109TPEL20132256371

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[29] W Yuan X C Huang J M Zhang and Z M Qian ldquoA Novel soft switchingflyback converter with synchronous rectificationrdquo in 2009 IEEE 6th Internatio-nal Power Electronics and Motion Control Conference May 2009 pp 551ndash555 doi101109IPEMC20095157448

[30] X Huang W Du W Yuan J Zhang and Z Qian ldquoA novel variable frequencysoft switching method for Flyback converter with synchronous rectifierrdquo in2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposi-tion (APEC) February 2010 pp 1392ndash1396 doi 101109APEC20105433411

[31] R Nalepa and N Barry and P Meaney ldquoPrimary side control circuit of aflyback converterrdquo in APEC 2001 Sixteenth Annual IEEE Applied Power Electro-nics Conference and Exposition (Cat No01CH37181) vol 1 March 2001 542ndash547vol1 doi 101109APEC2001911699

[32] Y Chen C Chang and P Yang ldquoA Novel Primary-Side Controlled Universal-Input AC-DC LED Driver Based on a Source-Driving Control Schemerdquo IEEETransactions on Power Electronics vol 30 no 8 pp 4327ndash4335 August 2015issn 0885-8993 doi 101109TPEL20142359585

[33] C-W Chang and Y-Y Tzou ldquoPrimary-side sensing error analysis for flybackconvertersrdquo in 2009 IEEE 6th International Power Electronics and Motion ControlConference May 2009 pp 524ndash528 doi 101109IPEMC20095157443

[34] Linear Technology LT8309 - Secondary Side Synchronous Rectifier Driver httpwwwlinearcomproductLT8309 Accessed May 2017

[35] Power Integrations TM Innoswitch CPhttpsac-dcpowercomproductsinnoswitch-familyinnoswitch-cp Accessed June 2017

[36] Power Integrations Design Example Report 65W Adapter Using TOPSwitch-JXTOP269EG httpsac-dcpowercomsitesdefaultfilesPDFFilesder243pdf Accessed January 2010

[37] Texas Instruments 65W (130W Surge) Flyback Power Supply for Laptop Adap-ter Apps w85-265VAC Input Reference Design httpwwwticomtoolPMP9208 Accessed May 2017

[38] Power Integrations Design Example Report 65W Power Supply Using InnoSwitch3-CE INN3168C-H101 httpsac-dcpowercomsitesdefaultfilesPDFFilesder535pdf Accessed October 2017

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[39] Fairchild Semiconductor H11L1M 6-Pin DIP Schmitt Trigger Output Opto-coupler httpswwwfairchildsemicomproductsoptoelectronicshigh-performance-optocouplershigh-speed-logic-gateH11L1MhtmlAccessed March 2017

[40] B Mahato P R Thakura and K C Jana ldquoHardware design and implemen-tation of Unity Power Factor Rectifiers using microcontrollersrdquo in 2014 IEEE6th India International Conference on Power Electronics (IICPE) December 2014pp 1ndash5 doi 101109IICPE20147115812

[41] B Chen ldquoIsolation in Digital Power Supplies Using Micro-Transformersrdquoin 2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference andExposition February 2009 pp 2039ndash2042 doi 101109APEC20094802954

[42] H Chen and J Xiao ldquoDetermination of Transformer Shielding Foil Structurefor Suppressing Common-Mode Noise in Flyback Convertersrdquo IEEE Tran-sactions on Magnetics vol 52 no 12 pp 1ndash9 Dec 2016 issn 0018-9464 doi101109TMAG20162594047

[43] G Spiazzi A Zuccato and P Tenti ldquoAnalysis of conducted and radiatednoise of soft-switched flyback DC-DC converterrdquo in Telecommunications EnergyConference 1996 INTELEC rsquo96 18th International October 1996 pp 297ndash304doi 101109INTLEC1996573328

[44] W H Yang C H Lin K H Chen C L Wey Y H Lin J R Lin T Y Tsai andJ L Chen ldquo95 light-load efficiency single-inductor dual-output DC-DC buckconverter with synthesized waveform control technique for USB Type-Crdquo in2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) June 2016 pp 1ndash2 doi101109VLSIC20167573476

[45] USBorg Introduction to USB-PD http www usb org developers powerdeliveryPD_10_Introductionpdf Accessed January 2017

[46] mdashmdash Specifications of USB-PD httpwwwusborgdevelopersdocsusb_31_021517zip Accessed January 2017

[47] Texas Instruments USB Type C and USB PD Source Controller httpwwwticomlitdsslvsdg8aslvsdg8apdf Accessed May 2016

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[48] Y Xi P K Jain and G Joos ldquoA zero voltage switching flyback convertertopologyrdquo in PESC97 Record 28th Annual IEEE Power Electronics SpecialistsConference Formerly Power Conditioning Specialists Conference 1970-71 PowerProcessing and Electronic Specialists Conference 1972 vol 2 June 1997 951ndash957vol2 doi 101109PESC1997616838

[49] X Yuan N Oswald and P Mellor ldquoSuperjunction MOSFETs in Voltage-SourceThree-Level Converters Experimental Investigation of Dynamic Behavior andSwitching Lossesrdquo IEEE Transactions on Power Electronics vol 30 no 12pp 6495ndash6501 December 2015 issn 0885-8993 doi 101109TPEL20152434877

[50] K Gauen ldquoThe effects of MOSFET output capacitance in high frequency ap-plicationsrdquo in Conference Record of the IEEE Industry Applications Society AnnualMeeting October 1989 1227ndash1234 vol2 doi 101109IAS198996800

[51] H Hu W Al-Hoor N H Kutkut I Batarseh and Z J Shen ldquoEfficiency Impro-vement of Grid-Tied Inverters at Low Input Power Using Pulse-Skipping Con-trol Strategyrdquo IEEE Transactions on Power Electronics vol 25 no 12 pp 3129ndash3138 December 2010 issn 0885-8993 doi 101109TPEL20102080690

[52] C Marxgut F Krismer D Bortis and J W Kolar ldquoUltraflat Interleaved Tri-angular Current Mode (TCM) Single-Phase PFC Rectifierrdquo IEEE Transactionson Power Electronics vol 29 no 2 pp 873ndash882 February 2014 issn 0885-8993doi 101109TPEL20132258941

[53] T H Chen and W L Lin and C M Liaw ldquoDynamic modeling and control-ler design of flyback converterrdquo IEEE Transactions on Aerospace and Electro-nic Systems vol 35 no 4 pp 1230ndash1239 October 1999 issn 0018-9251 doi1011097805441

[54] M K Kazimierczuk and S T Nguyen ldquoSmall-signal analysis of open-loopPWM flyback dc-dc converter for CCMrdquo Proceedings of the IEEE 1995 NationalAerospace and Electronics Conference NAECON 1995 vol 1 69ndash76 vol1 May1995 issn 0547-3578 doi 101109NAECON1995521914

[55] X Xie and C Zhao and Q Lu and S Liu ldquoA Novel Integrated Buck-FlybackNonisolated PFC Converter With High Power Factorrdquo IEEE Transactions onIndustrial Electronics vol 60 no 12 pp 5603ndash5612 December 2013 issn 0278-0046 doi 101109TIE20122232256

130

BIBLIOGRAPHY

[56] J G Hayes D Cashman M G Egan T OrsquoDonnell and N Wang ldquoComparisonof Test Methods for Characterization of High-Leakage Two-Winding Transfor-mersrdquo IEEE Transactions on Industry Applications vol 45 no 5 pp 1729ndash1741September 2009 issn 0093-9994 doi 101109TIA20092027549

[57] K I Hwu and Y H Chen ldquoEstimation of individual leakage inductances of atransformer based on measurementsrdquo in 2008 IEEE International Conference onIndustrial Technology April 2008 pp 1ndash3 doi 101109ICIT20084608452

[58] Texas Instruments TPS65982 USB Type-C and USB PD Controller httpwwwticomlitdssymlinktps65982pdf Accessed August 2016

[59] Mathworks Matlab httpswwwmathworkscom Accessed February2017

[60] Gecko Circuits Gecko simulations httpwwwgecko-simulationscomgeckocircuitshtml Accessed February 2017

[61] X Huang J Feng F C Lee Q Li and Y Yang ldquoConducted EMI analysisand filter design for MHz active clamp flyback front-end converterrdquo in 2016IEEE Applied Power Electronics Conference and Exposition (APEC) March 2016pp 1534ndash1540 doi 101109APEC20167468071

[62] AHesener Fairchild Semiconductor EMI in Power Supplies httpswwwfairchildsemicomtechnical-articlesElectromagnetic-Interference-

EMI-in-Power-Suppliespdf Accessed January 2017

[63] CENELEC Industry Standards EN 55016-2-2 2011

[64] K Raggl T Nussbaumer and J W Kolar ldquoGuideline for a Simplified Differential-Mode EMI Filter Designrdquo IEEE Transactions on Industrial Electronics vol 57no 3 pp 1031ndash1040 March 2010 issn 0278-0046 doi 101109TIE20092028293

[65] R Wang D Boroyevich H F Blanchette and P Mattavelli ldquoHigh powerdensity EMI filter design with consideration of self-parasiticrdquo in 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC)February 2012 pp 2285ndash2289 doi 101109APEC20126166141

[66] Optek TT Electronics PLC High Speed Opto-Isolator OPTI1268S Accessed Sep-tember 2015 [Online] Available 5Curl 7B 22http optekinc com datasheetsopi1268spdf227D

131

BIBLIOGRAPHY

[67] Texas Instruments 5V High Speed Digital Isolators httpwwwticomlitdssymlinkiso721m-eppdf Accessed June 2008

[68] Ferroxcube 3C96 Material Specification Datasheet httpwwwferroxcubecom Accessed January 2018

[69] Fluke Corporation Power Analyzers - Fluke Norma 40005000 httpwwwflukecomFlukeinenPower-Quality-ToolsHigh-Precision-Power-

AnalyzersFluke-Norma-4000-5000htmPID=56163 Accessed May 2017

[70] W Konrad and G Deboy and A Muetze ldquoA Power Supply Achieving Tita-nium Level Efficiency for a Wide Range of Input Voltagesrdquo IEEE Transactionson Power Electronics vol 32 no 1 pp 117ndash127 January 2017 issn 0885-8993doi 101109TPEL20162532962

[71] C Larouci and J P Ferrieux and L Gerbaud and J Roudet and S CatellanildquoExperimental evaluation of the core losses in the magnetic components usedin PFC converters Application to optimize the flyback structure lossesrdquo inAPEC Seventeenth Annual IEEE Applied Power Electronics Conference and Expo-sition vol 1 March 2002 326ndash331 vol1 doi 101109APEC2002989266

[72] M Pavlovsky and S W H de Haan and J A Ferreira ldquoPartial Interleaving AMethod to Reduce High Frequency Losses and to Tune the Leakage Inductancein High Current High Frequency Transformer Foil Windingsrdquo in 2005 IEEE36th Power Electronics Specialists Conference June 2005 pp 1540ndash1547 doi 101109PESC20051581835

[73] International Rectifier IR1169S Advanced SmartRectifier Control IC httpswwwinfineoncomdgdlir1169pdf Accessed November 2013


[75] F F Edwin and W Xiao and V Khadkikar ldquoDynamic Modeling and Controlof Interleaved Flyback Module-Integrated Converter for PV Power Applicati-onsrdquo IEEE Transactions on Industrial Electronics vol 61 no 3 pp 1377ndash1388March 2014 issn 0278-0046 doi 101109TIE20132258309

132

BIBLIOGRAPHY

[76] D Leuenberger and J Biela ldquoAccurate and computationally efficient modelingof flyback transformer parasitics and their influence on converter lossesrdquo in2015 17th European Conference on Power Electronics and Applications (EPErsquo15ECCE-Europe) September 2015 pp 1ndash10 doi 101109EPE20157309194

[77] A Capitaine and G Pillonnet and T Chailloux and F Khaled and O Ondeland B Allard ldquoLoss analysis of flyback in discontinuous conduction modefor sub-mW harvesting systemsrdquo in 2016 14th IEEE International New Circuitsand Systems Conference (NEWCAS) June 2016 pp 1ndash4 doi 101109NEWCAS20167604810

[78] J Li and F B M van Horck and B J Daniel and H J Bergveld ldquoA High-Switching-Frequency Flyback Converter in Resonant Moderdquo IEEE Transactionson Power Electronics vol 32 no 11 pp 8582ndash8592 November 2017 issn 0885-8993 doi 101109TPEL20162642044

[79] J W Yang and H L Do ldquoEfficient Single-Switch Boost-Dual-Input FlybackPFC Converter With Reduced Switching Lossrdquo IEEE Transactions on IndustrialElectronics vol 62 no 12 pp 7460ndash7468 December 2015 issn 0278-0046 doi101109TIE20152453938

[80] D Murthy-Bellur and N Kondrath and M K Kazimierczuk ldquoTransformerwinding loss caused by skin and proximity effects including harmonics inpulse-width modulated DC-DC flyback converters for the continuous con-duction moderdquo IET Power Electronics vol 4 no 4 pp 363ndash373 April 2011issn 1755-4535 doi 101049iet-pel20100040

[81] A Connaughton and A Talei and K Leong and K Krischan and A MuetzeldquoInvestigation of a Soft-Switching Flyback Converter with Full Secondary SideBased Controlrdquo IEEE Transactions on Industry Applications vol PP no 99 June2017 issn 0093-9994 doi 101109TIA20172730158

[82] T Halder ldquoPI Controller Tuning Amp Stability Analysis of the Flyback SMPSrdquoin 2014 IEEE 6th India International Conference on Power Electronics (IICPE)December 2014 pp 1ndash6 doi 101109IICPE20147115732

[83] W Iihoshi and K Nishijima and T Matsushita and S Teramoto ldquoDC outletusing a multi-output current resonant converterrdquo in 2015 IEEE InternationalTelecommunications Energy Conference (INTELEC) October 2015 pp 1ndash5 doi101109INTLEC20157572321

133

BIBLIOGRAPHY

[84] Texas Instruments A Primer on USB Type-C and Power Delivery Applicationsand Requirements httpwwwticomlitwpslyy109slyy109pdfAccessed October 2017

[85] mdashmdash Designs for Supporting Voltages in USB-PD Power Rules httpwwwticomlitanslva782slva782pdf Accessed October 2017

[86] D N Pattanayak and O G Tornblad ldquoLarge-signal and small-signal outputcapacitances of super junction MOSFETsrdquo in 2013 25th International Symposiumon Power Semiconductor Devices ICrsquos (ISPSD) May 2013 pp 229ndash232 doi 101109ISPSD20136694458

[87] G Deboy and O Haeberlen and M Treu ldquoPerspective of loss mechanismsfor silicon and wide band-gap power devicesrdquo CPSS Transactions on PowerElectronics and Applications vol 2 no 2 pp 89ndash100 August 2017 issn 2475-742X doi 1024295CPSSTPEA201700010

[88] He Li and Chengcheng Yao and Lixing Fu and Xuan Zhang and Jin WangldquoEvaluations and applications of GaN HEMTs for power electronicsrdquo in 2016IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia) May 2016 pp 563ndash569 doi 101109IPEMC20167512348

[89] X Huang and J Feng and W Du and F C Lee and Q Li ldquoDesign considerationof MHz active clamp flyback converter with GaN devices for low power adap-ter applicationrdquo in 2016 IEEE Applied Power Electronics Conference and Exposition(APEC) March 2016 pp 2334ndash2341 doi 101109APEC20167468191

134

Appendix A

List of Experimental Equipment

This appendix details the equipment used to make the measurements given throughout the

thesis The measurements corresponding to each piece of equipment are also listed

All switching frequencies and times were inferred using waveforms on the LeCroy HDO6104-MS oscilloscope and all efficiency measurements were performed using the FLUKE

Norma 5000 power analyzer Tab A1 lists the measurement equipment used All voltage

and current measurements presented in this thesis are listed in Tab A2 along with the

corresponding probes used in conjunction with the HDO 6104-MS

Table A1 Experimental equipment

Type Company Instrument Key Specrsquos

Passive Voltage Probe LeCroy PP008 400 VRMSDifferential Voltage Probe LeCroy ADP305 1400 VDifferential Voltage Probe LeCroy ZD200 plusmn 20 V

Current Probe LeCroy CP031 plusmn 30 ADigital Signal Probe (16 Ch) LeCroy MSO-DLS-001 plusmn 30 V

Oscilloscope (4 Ch) LeCroy HDO 6104-MS 25 GSsPower Analyzer (6 Ch) FLUKE Norma 5000 -

AC Voltage Supply iTech IT7321 300 VRMS 300 WDC Voltage Supply AIM-TTI EX453RD 35 V

135

Appendix A List of Experimental Equipment

Table A2 Measurements and corresponding probes

Fig PP008 ADP305 ZD200 CP031 MSO-DLS-001

52 QPRI VGS(S1) VDS(S1) - - -511 - VDS(S1) - iL2 -512 VOUT - - iL2 -513 VDS(S2) VDS(S1) Gate Comp - -517 - VDS(S1) Gate Comp - -515 - VDS(S1) Gate Comp - -516 - VDS(S1) Gate Comp - -518 VOUT VDS(S1) - - -519 - VDS(S1) GateSEC - -

612 Qslope Qqzvs VDS(S1) - iL2 -613 Qslope Qqzvs VDS(S1) - iL2 -614 VOUT QSR - - iL2 -615 VOUT QSR - - iL2 -616 - VDS(S1) - iL2 -617 - VDC-link - iL2 -618 VOUT - - iL2 -619 VOUT - - iL2 -620 - - - iL2 -621 VOUT - - iOUT -622 - - - iOUT iL2 -

71 VDS(S2) - - iL1 iL2 -73 VDS(S2) - - iL1 iL2 QOUT QSOFT S277 - VDC-link - - -78 - VDC-link - - -79 - VDC-link - - -714 - VDS(S1) - iL1 iL2 S1 S2715 VOUT - - iL2 -

136

Abstract

Zusammenfassung (Abstract in German)

Acknowledgements

Overview

Thesis Objectives

Credit and Contributions to State of the Art

Related Publications

Structure of Thesis

Introduction

Flyback Converter Topology

Comparison to Other Topologies

Fundamentals of Operation

Applications

Active Synchronous Rectification

Important Flyback Design Considerations

Devices MOSFETs

Structure

Behaviour and Characteristics

Soft Switching

Classic and State-of-the-Art Control Concepts

Classic Flyback Control

Primary Side Regulation

Single IC Cross-Barrier Solutions

Flyback Efficiency

Secondary Side Controlled Flyback Concept

Chapter Outline

Concept Overview

Comparison to State-of-the-Art

Turn-ON Requests from Secondary Side

Steady State Operation

Proving the Feasibility of the Secondary Side Controlled Flyback Concept

Chapter Outline

Voltage Sensing

Primary Side Switch ndash Double Pulse Response

Secondary Side ndash Synchronous Rectification

Secondary Side ndash Output Voltage

Constant ON-Time Control

High- and Low-Line Input Voltage

Coupled Inductor Design

Start-Up Routine and Primary Logic

65 W Demonstrator Hardware ndash SSCF1

Control Boards


Power Board

Sensing ndash Passive Component Parameters

Experimental Results

Steady-State COT Operation

Primary Side Drain-Source Sensing Behaviour

Start-Up Routine

Efficiency Measurements

Loss Breakdown

Effect of Proposed Secondary Side Control on Efficiency

Effect of Non-Optimal Coupled Inductor on Efficiency

Effect of COT Control on Efficiency

Conclusion

Improving the Viability of the Secondary Side Controlled Flyback

Chapter Outline

Q-ZVS Improvement

Calculation of Negative Current Time

Primary Side Drain-Source Voltage Sensing

Synchronous Rectification Improvement

Variable-ON-Time Control

Proposed Concept

Split Control Structure

Start-Up Routine

Calculating Inductances for VOT Control


150 kHz Power Board

Control and Adapter Boards


EMI-Filter for VOT

Drain-Source Voltage Sensing

SSCF2 VDS Sensing Measurements

Primary Side

Secondary Side

VOT Measurements


Load Jumps

Natural Current Limiting

Efficiency Losses and Frequency Variation

Measurements

Switching Frequency Variation

Conclusions

Expanding the Capability of the Secondary Side Controlled Flyback

Chapter Outline

Soft Negative Current Turn-ON Requests

Effects of Irregular Secondary Turn-ON Voltage

Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept

Hardware and Control Set-Up

Measured Switching Frequency and ON-time Behaviour

Efficiency

Reverse Power Flow for Multiple Output Voltages

Proposed Concept

Secondary Side VOT for Safe Reverse Power Flow

Constraints on Minimum Negative Current Time

Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability

Outlook Short Term Further Work

Outlook Wide Band Gap Devices

Turn-ON Request Loss

Reverse Power Flow

Symbols and Abbreviations

Bibliography


AFFIDAVIT

I declare that I have authored this thesis independently that I have not used otherthan the declared sourcesresources and that I have explicitly indicated all materialwhich has been quoted either literally or by content from the sources used Moreoverthe electronic version of this document uploaded to TUGRAZonline is identical tothis printed version

Date Signature


Contents

Abstract V


Acknowledgements IX








213 Applications 10




221 Structure 14







I

Contents







56 Conclusion 65


II

Contents








69 Conclusions 94




III

Contents



75 Conclusion 114






Bibliography 125


IV

Abstract




V

Zusammenfassung


VII

Acknowledgements









Thank you all

IX

Chapter 1

Overview









1

Chapter 1 Overview











2







ISSN 0093-9994








March 2016




3

Chapter 1 Overview






4

Chapter 2

Introduction




COUT

S1

L2L1

D0

Input

Output

CIN


5

















6





S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN


S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN




φ = φ0 +VIN

N1tON (21)


7








φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)


VOUT =N2

N1

D1 minusD

VIN (26)



iL1 = iL1(0) +VIN

L1tON (27)


8



iL2 =N1

N2iL1 = N iL1 (28)


N =N1

N2=

radicL1

L2(29)


VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)


VDS(S1) = VIN +N1

N2VOUT (212)





9


213 Applications



COUT

S1

L2L1

UGRID

D0

CDC-link




10




COUT

S1

S2

L2L1

UGRID

CDC-link





11




Switching Frequency








Coupled Inductor


12


Snubber


S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT



Input EMI-Filter


13


22 Devices MOSFETs


221 Structure


G

D

S S

n+ n+

p p

n-

n+


G

D

S S

n+ n+

p p

n-

n+

p+p+



14

22 Devices MOSFETs





G

D

S

CGD

CGS

CDS



15



G

D

S S

n+ n+

p p

n-

n+

p+p+






16

22 Devices MOSFETs


223 Soft Switching



17

Chapter 3










19




S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER




20





S1

L2COUT

L1 VOUT

D0

CDC-link



S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link





21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time


S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time



22




VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)


L2

L2+Lσ2Lm


VOUT =N2





23







24




0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()





25

Chapter 4


41 Chapter Outline


27


42 Concept Overview


S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED


CONTROLLER




28










29



S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side


Slave Logic




30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold



QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic





31




gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST


32

Chapter 5


51 Chapter Outline










33


52 Voltage Sensing




minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2



34

52 Voltage Sensing





05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)



35








R2lt C1

dVDS(S1)

dt(51)




36

52 Voltage Sensing



R3minus

+

S2

QSR

D4

D5




COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2


37




gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold



38






N

Y

S2 ON


Y


Y

N


S2 OFF


N

Y

S2 ONS2 OFF

Pulse-skipping


Turn-ON Request


39




TON =

radic2L1PIN


(52)





40





2minus

Prated

CDC-link f grid(53)



Pneg =12





L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)


41










42





Connect to Grid


Send lowpower pulse

Wait


N

Y


Wait

Sample VOUT


N

Y


Send turn-ONrequest


N

Y

Enter Steady State


Y


43




541 Control Boards






44




1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)










45


543 Power Board


Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link







46


S1Driver

Diode Bridge


Sensing

S2Driver

Snubber Diode

AdditionalCOUT








47
















48



















49





106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)




50




0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2





51




Device Stresses



S1 S2 Occurs during






52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)





53





20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro





54







55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



56







FPGA 37 37



TOTAL 113 111



57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)






58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)



14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo


t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)



59




0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()






60


555 Loss Breakdown






61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore


Other


10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate



S2 condS2 gate


62


Leakage Inductance




σ 284microH


Core Material




63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other


64

56 Conclusion



56 Conclusion




65






66

Chapter 6


61 Chapter Outline







67






gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS


68




QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)



INEG =





69





C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6



R8

C5

minus+

minus

+

Qslope

UslopeS1


70



C5d VDS(S1)

dtgt

Uslope

R8(65)





R9

C6

minus

+

minus

+

S2

SSF

QSR

USF




71





tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts


72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired





73



gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait



TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)


74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R




S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link


Regulation




75





2minus

POUT

CDC-link f grid(67)


Pneg =12




L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)


76





Coupled Inductor

S2

Secondary Side

COUT


Input EMI-Filter








77






Power Board

AC InputConnections


Auxilliary Voltages






78














79














80














81



661 Primary Side


0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)





82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)



662 Secondary Side





83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



84

67 VOT Measurements

67 VOT Measurements












85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)



0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)



86

67 VOT Measurements


870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)



672 Load Jumps


87




0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)





88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)






89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)



220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k



90



681 Measurements






0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding







92



20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)







93


69 Conclusions








94

Chapter 7


71 Chapter Outline





95





0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)




96









722 Hardware


R10

R11

minus

+

minus

+

S2

QSOFT

USOFT


97






0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)



98






20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq




99


724 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()


Low-LineHigh-Line



100

73 VF-VOT Concept

73 VF-VOT Concept



Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER


101












102

73 VF-VOT Concept




0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)





103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept



20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S



105


734 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()





106

73 VF-VOT Concept



0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()


Falling FREF


107










108












109



gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT


tNEG(R)++

20 V VOUTthreshold


tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1


110





L1 VOUTTLOWER (71)


0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)





111



tNEG(R) gt1

VOUT



744 Measurements







112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V






113


75 Conclusion





114

Chapter 8

Conclusions

81 Summary








115


811 Feasibility




812 Viability


116

81 Summary




813 Capability



117













118








119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF




0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS


e-mode GaN 52 mΩ



120


Abbreviations









121


Symbols

Component Parameter
































id A Drain current

122














PIN W Input power

Ploss W Power loss






















123






































124

Bibliography











125

BIBLIOGRAPHY










126

BIBLIOGRAPHY











127

BIBLIOGRAPHY











128

BIBLIOGRAPHY










129

BIBLIOGRAPHY









130

BIBLIOGRAPHY













131

BIBLIOGRAPHY











132

BIBLIOGRAPHY









133

BIBLIOGRAPHY







134

Appendix A














135







136

Abstract


Acknowledgements

Overview

Thesis Objectives



Structure of Thesis

Introduction




Applications



Devices MOSFETs

Structure


Soft Switching





Flyback Efficiency


Chapter Outline

Concept Overview





Chapter Outline

Voltage Sensing









Control Boards


Power Board





Start-Up Routine


Loss Breakdown




Conclusion


Chapter Outline

Q-ZVS Improvement





Proposed Concept


Start-Up Routine



150 kHz Power Board



EMI-Filter for VOT



Primary Side

Secondary Side

VOT Measurements


Load Jumps



Measurements


Conclusions


Chapter Outline



Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept



Efficiency


Proposed Concept



Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability




Reverse Power Flow


Bibliography



Contents

Abstract V


Acknowledgements IX








213 Applications 10




221 Structure 14







I

Contents







56 Conclusion 65


II

Contents








69 Conclusions 94




III

Contents



75 Conclusion 114






Bibliography 125


IV

Abstract




V

Zusammenfassung


VII

Acknowledgements









Thank you all

IX

Chapter 1

Overview









1

Chapter 1 Overview











2







ISSN 0093-9994








March 2016




3

Chapter 1 Overview






4

Chapter 2

Introduction




COUT

S1

L2L1

D0

Input

Output

CIN


5

















6





S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN


S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN




φ = φ0 +VIN

N1tON (21)


7








φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)


VOUT =N2

N1

D1 minusD

VIN (26)



iL1 = iL1(0) +VIN

L1tON (27)


8



iL2 =N1

N2iL1 = N iL1 (28)


N =N1

N2=

radicL1

L2(29)


VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)


VDS(S1) = VIN +N1

N2VOUT (212)





9


213 Applications



COUT

S1

L2L1

UGRID

D0

CDC-link




10




COUT

S1

S2

L2L1

UGRID

CDC-link





11




Switching Frequency








Coupled Inductor


12


Snubber


S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT



Input EMI-Filter


13


22 Devices MOSFETs


221 Structure


G

D

S S

n+ n+

p p

n-

n+


G

D

S S

n+ n+

p p

n-

n+

p+p+



14

22 Devices MOSFETs





G

D

S

CGD

CGS

CDS



15



G

D

S S

n+ n+

p p

n-

n+

p+p+






16

22 Devices MOSFETs


223 Soft Switching



17

Chapter 3










19




S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER




20





S1

L2COUT

L1 VOUT

D0

CDC-link



S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link





21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time


S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time



22




VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)


L2

L2+Lσ2Lm


VOUT =N2





23







24




0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()





25

Chapter 4


41 Chapter Outline


27


42 Concept Overview


S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED


CONTROLLER




28










29



S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side


Slave Logic




30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold



QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic





31




gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST


32

Chapter 5


51 Chapter Outline










33


52 Voltage Sensing




minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2



34

52 Voltage Sensing





05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)



35








R2lt C1

dVDS(S1)

dt(51)




36

52 Voltage Sensing



R3minus

+

S2

QSR

D4

D5




COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2


37




gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold



38






N

Y

S2 ON


Y


Y

N


S2 OFF


N

Y

S2 ONS2 OFF

Pulse-skipping


Turn-ON Request


39




TON =

radic2L1PIN


(52)





40





2minus

Prated

CDC-link f grid(53)



Pneg =12





L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)


41










42





Connect to Grid


Send lowpower pulse

Wait


N

Y


Wait

Sample VOUT


N

Y


Send turn-ONrequest


N

Y

Enter Steady State


Y


43




541 Control Boards






44




1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)










45


543 Power Board


Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link







46


S1Driver

Diode Bridge


Sensing

S2Driver

Snubber Diode

AdditionalCOUT








47
















48



















49





106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)




50




0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2





51




Device Stresses



S1 S2 Occurs during






52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)





53





20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro





54







55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



56







FPGA 37 37



TOTAL 113 111



57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)






58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)



14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo


t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)



59




0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()






60


555 Loss Breakdown






61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore


Other


10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate



S2 condS2 gate


62


Leakage Inductance




σ 284microH


Core Material




63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other


64

56 Conclusion



56 Conclusion




65






66

Chapter 6


61 Chapter Outline







67






gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS


68




QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)



INEG =





69





C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6



R8

C5

minus+

minus

+

Qslope

UslopeS1


70



C5d VDS(S1)

dtgt

Uslope

R8(65)





R9

C6

minus

+

minus

+

S2

SSF

QSR

USF




71





tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts


72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired





73



gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait



TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)


74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R




S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link


Regulation




75





2minus

POUT

CDC-link f grid(67)


Pneg =12




L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)


76





Coupled Inductor

S2

Secondary Side

COUT


Input EMI-Filter








77






Power Board

AC InputConnections


Auxilliary Voltages






78














79














80














81



661 Primary Side


0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)





82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)



662 Secondary Side





83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



84

67 VOT Measurements

67 VOT Measurements












85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)



0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)



86

67 VOT Measurements


870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)



672 Load Jumps


87




0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)





88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)






89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)



220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k



90



681 Measurements






0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding







92



20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)







93


69 Conclusions








94

Chapter 7


71 Chapter Outline





95





0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)




96









722 Hardware


R10

R11

minus

+

minus

+

S2

QSOFT

USOFT


97






0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)



98






20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq




99


724 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()


Low-LineHigh-Line



100

73 VF-VOT Concept

73 VF-VOT Concept



Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER


101












102

73 VF-VOT Concept




0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)





103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept



20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S



105


734 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()





106

73 VF-VOT Concept



0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()


Falling FREF


107










108












109



gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT


tNEG(R)++

20 V VOUTthreshold


tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1


110





L1 VOUTTLOWER (71)


0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)





111



tNEG(R) gt1

VOUT



744 Measurements







112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V






113


75 Conclusion





114

Chapter 8

Conclusions

81 Summary








115


811 Feasibility




812 Viability


116

81 Summary




813 Capability



117













118








119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF




0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS


e-mode GaN 52 mΩ



120


Abbreviations









121


Symbols

Component Parameter
































id A Drain current

122














PIN W Input power

Ploss W Power loss






















123






































124

Bibliography











125

BIBLIOGRAPHY










126

BIBLIOGRAPHY











127

BIBLIOGRAPHY











128

BIBLIOGRAPHY










129

BIBLIOGRAPHY









130

BIBLIOGRAPHY













131

BIBLIOGRAPHY











132

BIBLIOGRAPHY









133

BIBLIOGRAPHY







134

Appendix A














135







136

Abstract


Acknowledgements

Overview

Thesis Objectives



Structure of Thesis

Introduction




Applications



Devices MOSFETs

Structure


Soft Switching





Flyback Efficiency


Chapter Outline

Concept Overview





Chapter Outline

Voltage Sensing









Control Boards


Power Board





Start-Up Routine


Loss Breakdown




Conclusion


Chapter Outline

Q-ZVS Improvement





Proposed Concept


Start-Up Routine



150 kHz Power Board



EMI-Filter for VOT



Primary Side

Secondary Side

VOT Measurements


Load Jumps



Measurements


Conclusions


Chapter Outline



Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept



Efficiency


Proposed Concept



Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability




Reverse Power Flow


Bibliography


Contents







56 Conclusion 65


II

Contents








69 Conclusions 94




III

Contents



75 Conclusion 114






Bibliography 125


IV

Abstract




V

Zusammenfassung


VII

Acknowledgements









Thank you all

IX

Chapter 1

Overview









1

Chapter 1 Overview











2







ISSN 0093-9994








March 2016




3

Chapter 1 Overview






4

Chapter 2

Introduction




COUT

S1

L2L1

D0

Input

Output

CIN


5

















6





S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN


S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN




φ = φ0 +VIN

N1tON (21)


7








φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)


VOUT =N2

N1

D1 minusD

VIN (26)



iL1 = iL1(0) +VIN

L1tON (27)


8



iL2 =N1

N2iL1 = N iL1 (28)


N =N1

N2=

radicL1

L2(29)


VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)


VDS(S1) = VIN +N1

N2VOUT (212)





9


213 Applications



COUT

S1

L2L1

UGRID

D0

CDC-link




10




COUT

S1

S2

L2L1

UGRID

CDC-link





11




Switching Frequency








Coupled Inductor


12


Snubber


S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT



Input EMI-Filter


13


22 Devices MOSFETs


221 Structure


G

D

S S

n+ n+

p p

n-

n+


G

D

S S

n+ n+

p p

n-

n+

p+p+



14

22 Devices MOSFETs





G

D

S

CGD

CGS

CDS



15



G

D

S S

n+ n+

p p

n-

n+

p+p+






16

22 Devices MOSFETs


223 Soft Switching



17

Chapter 3










19




S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER




20





S1

L2COUT

L1 VOUT

D0

CDC-link



S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link





21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time


S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time



22




VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)


L2

L2+Lσ2Lm


VOUT =N2





23







24




0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()





25

Chapter 4


41 Chapter Outline


27


42 Concept Overview


S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED


CONTROLLER




28










29



S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side


Slave Logic




30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold



QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic





31




gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST


32

Chapter 5


51 Chapter Outline










33


52 Voltage Sensing




minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2



34

52 Voltage Sensing





05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)



35








R2lt C1

dVDS(S1)

dt(51)




36

52 Voltage Sensing



R3minus

+

S2

QSR

D4

D5




COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2


37




gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold



38






N

Y

S2 ON


Y


Y

N


S2 OFF


N

Y

S2 ONS2 OFF

Pulse-skipping


Turn-ON Request


39




TON =

radic2L1PIN


(52)





40





2minus

Prated

CDC-link f grid(53)



Pneg =12





L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)


41










42





Connect to Grid


Send lowpower pulse

Wait


N

Y


Wait

Sample VOUT


N

Y


Send turn-ONrequest


N

Y

Enter Steady State


Y


43




541 Control Boards






44




1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)










45


543 Power Board


Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link







46


S1Driver

Diode Bridge


Sensing

S2Driver

Snubber Diode

AdditionalCOUT








47
















48



















49





106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)




50




0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2





51




Device Stresses



S1 S2 Occurs during






52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)





53





20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro





54







55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



56







FPGA 37 37



TOTAL 113 111



57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)






58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)



14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo


t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)



59




0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()






60


555 Loss Breakdown






61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore


Other


10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate



S2 condS2 gate


62


Leakage Inductance




σ 284microH


Core Material




63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other


64

56 Conclusion



56 Conclusion




65






66

Chapter 6


61 Chapter Outline







67






gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS


68




QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)



INEG =





69





C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6



R8

C5

minus+

minus

+

Qslope

UslopeS1


70



C5d VDS(S1)

dtgt

Uslope

R8(65)





R9

C6

minus

+

minus

+

S2

SSF

QSR

USF




71





tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts


72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired





73



gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait



TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)


74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R




S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link


Regulation




75





2minus

POUT

CDC-link f grid(67)


Pneg =12




L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)


76





Coupled Inductor

S2

Secondary Side

COUT


Input EMI-Filter








77






Power Board

AC InputConnections


Auxilliary Voltages






78














79














80














81



661 Primary Side


0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)





82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)



662 Secondary Side





83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



84

67 VOT Measurements

67 VOT Measurements












85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)



0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)



86

67 VOT Measurements


870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)



672 Load Jumps


87




0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)





88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)






89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)



220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k



90



681 Measurements






0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding







92



20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)







93


69 Conclusions








94

Chapter 7


71 Chapter Outline





95





0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)




96









722 Hardware


R10

R11

minus

+

minus

+

S2

QSOFT

USOFT


97






0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)



98






20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq




99


724 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()


Low-LineHigh-Line



100

73 VF-VOT Concept

73 VF-VOT Concept



Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER


101












102

73 VF-VOT Concept




0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)





103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept



20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S



105


734 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()





106

73 VF-VOT Concept



0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()


Falling FREF


107










108












109



gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT


tNEG(R)++

20 V VOUTthreshold


tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1


110





L1 VOUTTLOWER (71)


0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)





111



tNEG(R) gt1

VOUT



744 Measurements







112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V






113


75 Conclusion





114

Chapter 8

Conclusions

81 Summary








115


811 Feasibility




812 Viability


116

81 Summary




813 Capability



117













118








119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF




0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS


e-mode GaN 52 mΩ



120


Abbreviations









121


Symbols

Component Parameter
































id A Drain current

122














PIN W Input power

Ploss W Power loss






















123






































124

Bibliography











125

BIBLIOGRAPHY










126

BIBLIOGRAPHY











127

BIBLIOGRAPHY











128

BIBLIOGRAPHY










129

BIBLIOGRAPHY









130

BIBLIOGRAPHY













131

BIBLIOGRAPHY











132

BIBLIOGRAPHY









133

BIBLIOGRAPHY







134

Appendix A














135







136

Abstract


Acknowledgements

Overview

Thesis Objectives



Structure of Thesis

Introduction




Applications



Devices MOSFETs

Structure


Soft Switching





Flyback Efficiency


Chapter Outline

Concept Overview





Chapter Outline

Voltage Sensing









Control Boards


Power Board





Start-Up Routine


Loss Breakdown




Conclusion


Chapter Outline

Q-ZVS Improvement





Proposed Concept


Start-Up Routine



150 kHz Power Board



EMI-Filter for VOT



Primary Side

Secondary Side

VOT Measurements


Load Jumps



Measurements


Conclusions


Chapter Outline



Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept



Efficiency


Proposed Concept



Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability




Reverse Power Flow


Bibliography


Contents








69 Conclusions 94




III

Contents



75 Conclusion 114






Bibliography 125


IV

Abstract




V

Zusammenfassung


VII

Acknowledgements









Thank you all

IX

Chapter 1

Overview









1

Chapter 1 Overview











2







ISSN 0093-9994








March 2016




3

Chapter 1 Overview






4

Chapter 2

Introduction




COUT

S1

L2L1

D0

Input

Output

CIN


5

















6





S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN


S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN




φ = φ0 +VIN

N1tON (21)


7








φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)


VOUT =N2

N1

D1 minusD

VIN (26)



iL1 = iL1(0) +VIN

L1tON (27)


8



iL2 =N1

N2iL1 = N iL1 (28)


N =N1

N2=

radicL1

L2(29)


VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)


VDS(S1) = VIN +N1

N2VOUT (212)





9


213 Applications



COUT

S1

L2L1

UGRID

D0

CDC-link




10




COUT

S1

S2

L2L1

UGRID

CDC-link





11




Switching Frequency








Coupled Inductor


12


Snubber


S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT



Input EMI-Filter


13


22 Devices MOSFETs


221 Structure


G

D

S S

n+ n+

p p

n-

n+


G

D

S S

n+ n+

p p

n-

n+

p+p+



14

22 Devices MOSFETs





G

D

S

CGD

CGS

CDS



15



G

D

S S

n+ n+

p p

n-

n+

p+p+






16

22 Devices MOSFETs


223 Soft Switching



17

Chapter 3










19




S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER




20





S1

L2COUT

L1 VOUT

D0

CDC-link



S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link





21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time


S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time



22




VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)


L2

L2+Lσ2Lm


VOUT =N2





23







24




0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()





25

Chapter 4


41 Chapter Outline


27


42 Concept Overview


S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED


CONTROLLER




28










29



S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side


Slave Logic




30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold



QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic





31




gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST


32

Chapter 5


51 Chapter Outline










33


52 Voltage Sensing




minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2



34

52 Voltage Sensing





05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)



35








R2lt C1

dVDS(S1)

dt(51)




36

52 Voltage Sensing



R3minus

+

S2

QSR

D4

D5




COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2


37




gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold



38






N

Y

S2 ON


Y


Y

N


S2 OFF


N

Y

S2 ONS2 OFF

Pulse-skipping


Turn-ON Request


39




TON =

radic2L1PIN


(52)





40





2minus

Prated

CDC-link f grid(53)



Pneg =12





L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)


41










42





Connect to Grid


Send lowpower pulse

Wait


N

Y


Wait

Sample VOUT


N

Y


Send turn-ONrequest


N

Y

Enter Steady State


Y


43




541 Control Boards






44




1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)










45


543 Power Board


Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link







46


S1Driver

Diode Bridge


Sensing

S2Driver

Snubber Diode

AdditionalCOUT








47
















48



















49





106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)




50




0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2





51




Device Stresses



S1 S2 Occurs during






52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)





53





20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro





54







55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



56







FPGA 37 37



TOTAL 113 111



57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)






58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)



14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo


t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)



59




0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()






60


555 Loss Breakdown






61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore


Other


10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate



S2 condS2 gate


62


Leakage Inductance




σ 284microH


Core Material




63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other


64

56 Conclusion



56 Conclusion




65






66

Chapter 6


61 Chapter Outline







67






gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS


68




QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)



INEG =





69





C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6



R8

C5

minus+

minus

+

Qslope

UslopeS1


70



C5d VDS(S1)

dtgt

Uslope

R8(65)





R9

C6

minus

+

minus

+

S2

SSF

QSR

USF




71





tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts


72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired





73



gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait



TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)


74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R




S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link


Regulation




75





2minus

POUT

CDC-link f grid(67)


Pneg =12




L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)


76





Coupled Inductor

S2

Secondary Side

COUT


Input EMI-Filter








77






Power Board

AC InputConnections


Auxilliary Voltages






78














79














80














81



661 Primary Side


0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)





82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)



662 Secondary Side





83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



84

67 VOT Measurements

67 VOT Measurements












85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)



0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)



86

67 VOT Measurements


870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)



672 Load Jumps


87




0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)





88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)






89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)



220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k



90



681 Measurements






0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding







92



20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)







93


69 Conclusions








94

Chapter 7


71 Chapter Outline





95





0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)




96









722 Hardware


R10

R11

minus

+

minus

+

S2

QSOFT

USOFT


97






0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)



98






20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq




99


724 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()


Low-LineHigh-Line



100

73 VF-VOT Concept

73 VF-VOT Concept



Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER


101












102

73 VF-VOT Concept




0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)





103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept



20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S



105


734 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()





106

73 VF-VOT Concept



0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()


Falling FREF


107










108












109



gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT


tNEG(R)++

20 V VOUTthreshold


tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1


110





L1 VOUTTLOWER (71)


0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)





111



tNEG(R) gt1

VOUT



744 Measurements







112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V






113


75 Conclusion





114

Chapter 8

Conclusions

81 Summary








115


811 Feasibility




812 Viability


116

81 Summary




813 Capability



117













118








119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF




0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS


e-mode GaN 52 mΩ



120


Abbreviations









121


Symbols

Component Parameter
































id A Drain current

122














PIN W Input power

Ploss W Power loss






















123






































124

Bibliography











125

BIBLIOGRAPHY










126

BIBLIOGRAPHY











127

BIBLIOGRAPHY











128

BIBLIOGRAPHY










129

BIBLIOGRAPHY









130

BIBLIOGRAPHY













131

BIBLIOGRAPHY











132

BIBLIOGRAPHY









133

BIBLIOGRAPHY







134

Appendix A














135







136

Abstract


Acknowledgements

Overview

Thesis Objectives



Structure of Thesis

Introduction




Applications



Devices MOSFETs

Structure


Soft Switching





Flyback Efficiency


Chapter Outline

Concept Overview





Chapter Outline

Voltage Sensing









Control Boards


Power Board





Start-Up Routine


Loss Breakdown




Conclusion


Chapter Outline

Q-ZVS Improvement





Proposed Concept


Start-Up Routine



150 kHz Power Board



EMI-Filter for VOT



Primary Side

Secondary Side

VOT Measurements


Load Jumps



Measurements


Conclusions


Chapter Outline



Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept



Efficiency


Proposed Concept



Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability




Reverse Power Flow


Bibliography


Contents



75 Conclusion 114






Bibliography 125


IV

Abstract




V

Zusammenfassung


VII

Acknowledgements









Thank you all

IX

Chapter 1

Overview









1

Chapter 1 Overview











2







ISSN 0093-9994








March 2016




3

Chapter 1 Overview






4

Chapter 2

Introduction




COUT

S1

L2L1

D0

Input

Output

CIN


5

















6





S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN


S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN




φ = φ0 +VIN

N1tON (21)


7








φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)


VOUT =N2

N1

D1 minusD

VIN (26)



iL1 = iL1(0) +VIN

L1tON (27)


8



iL2 =N1

N2iL1 = N iL1 (28)


N =N1

N2=

radicL1

L2(29)


VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)


VDS(S1) = VIN +N1

N2VOUT (212)





9


213 Applications



COUT

S1

L2L1

UGRID

D0

CDC-link




10




COUT

S1

S2

L2L1

UGRID

CDC-link





11




Switching Frequency








Coupled Inductor


12


Snubber


S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT



Input EMI-Filter


13


22 Devices MOSFETs


221 Structure


G

D

S S

n+ n+

p p

n-

n+


G

D

S S

n+ n+

p p

n-

n+

p+p+



14

22 Devices MOSFETs





G

D

S

CGD

CGS

CDS



15



G

D

S S

n+ n+

p p

n-

n+

p+p+






16

22 Devices MOSFETs


223 Soft Switching



17

Chapter 3










19




S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER




20





S1

L2COUT

L1 VOUT

D0

CDC-link



S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link





21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time


S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time



22




VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)


L2

L2+Lσ2Lm


VOUT =N2





23







24




0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()





25

Chapter 4


41 Chapter Outline


27


42 Concept Overview


S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED


CONTROLLER




28










29



S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side


Slave Logic




30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold



QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic





31




gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST


32

Chapter 5


51 Chapter Outline










33


52 Voltage Sensing




minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2



34

52 Voltage Sensing





05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)



35








R2lt C1

dVDS(S1)

dt(51)




36

52 Voltage Sensing



R3minus

+

S2

QSR

D4

D5




COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2


37




gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold



38






N

Y

S2 ON


Y


Y

N


S2 OFF


N

Y

S2 ONS2 OFF

Pulse-skipping


Turn-ON Request


39




TON =

radic2L1PIN


(52)





40





2minus

Prated

CDC-link f grid(53)



Pneg =12





L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)


41










42





Connect to Grid


Send lowpower pulse

Wait


N

Y


Wait

Sample VOUT


N

Y


Send turn-ONrequest


N

Y

Enter Steady State


Y


43




541 Control Boards






44




1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)










45


543 Power Board


Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link







46


S1Driver

Diode Bridge


Sensing

S2Driver

Snubber Diode

AdditionalCOUT








47
















48



















49





106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)




50




0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2





51




Device Stresses



S1 S2 Occurs during






52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)





53





20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro





54







55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



56







FPGA 37 37



TOTAL 113 111



57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)






58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)



14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo


t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)



59




0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()






60


555 Loss Breakdown






61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore


Other


10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate



S2 condS2 gate


62


Leakage Inductance




σ 284microH


Core Material




63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other


64

56 Conclusion



56 Conclusion




65






66

Chapter 6


61 Chapter Outline







67






gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS


68




QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)



INEG =





69





C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6



R8

C5

minus+

minus

+

Qslope

UslopeS1


70



C5d VDS(S1)

dtgt

Uslope

R8(65)





R9

C6

minus

+

minus

+

S2

SSF

QSR

USF




71





tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts


72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired





73



gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait



TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)


74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R




S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link


Regulation




75





2minus

POUT

CDC-link f grid(67)


Pneg =12




L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)


76





Coupled Inductor

S2

Secondary Side

COUT


Input EMI-Filter








77






Power Board

AC InputConnections


Auxilliary Voltages






78














79














80














81



661 Primary Side


0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)





82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)



662 Secondary Side





83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



84

67 VOT Measurements

67 VOT Measurements












85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)



0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)



86

67 VOT Measurements


870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)



672 Load Jumps


87




0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)





88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)






89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)



220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k



90



681 Measurements






0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding







92



20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)







93


69 Conclusions








94

Chapter 7


71 Chapter Outline





95





0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)




96









722 Hardware


R10

R11

minus

+

minus

+

S2

QSOFT

USOFT


97






0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)



98






20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq




99


724 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()


Low-LineHigh-Line



100

73 VF-VOT Concept

73 VF-VOT Concept



Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER


101












102

73 VF-VOT Concept




0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)





103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept



20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S



105


734 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()





106

73 VF-VOT Concept



0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()


Falling FREF


107










108












109



gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT


tNEG(R)++

20 V VOUTthreshold


tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1


110





L1 VOUTTLOWER (71)


0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)





111



tNEG(R) gt1

VOUT



744 Measurements







112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V






113


75 Conclusion





114

Chapter 8

Conclusions

81 Summary








115


811 Feasibility




812 Viability


116

81 Summary




813 Capability



117













118








119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF




0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS


e-mode GaN 52 mΩ



120


Abbreviations









121


Symbols

Component Parameter
































id A Drain current

122














PIN W Input power

Ploss W Power loss






















123






































124

Bibliography











125

BIBLIOGRAPHY










126

BIBLIOGRAPHY











127

BIBLIOGRAPHY











128

BIBLIOGRAPHY










129

BIBLIOGRAPHY









130

BIBLIOGRAPHY













131

BIBLIOGRAPHY











132

BIBLIOGRAPHY









133

BIBLIOGRAPHY







134

Appendix A














135







136

Abstract


Acknowledgements

Overview

Thesis Objectives



Structure of Thesis

Introduction




Applications



Devices MOSFETs

Structure


Soft Switching





Flyback Efficiency


Chapter Outline

Concept Overview





Chapter Outline

Voltage Sensing









Control Boards


Power Board





Start-Up Routine


Loss Breakdown




Conclusion


Chapter Outline

Q-ZVS Improvement





Proposed Concept


Start-Up Routine



150 kHz Power Board



EMI-Filter for VOT



Primary Side

Secondary Side

VOT Measurements


Load Jumps



Measurements


Conclusions


Chapter Outline



Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept



Efficiency


Proposed Concept



Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability




Reverse Power Flow


Bibliography


Abstract




V

Zusammenfassung


VII

Acknowledgements









Thank you all

IX

Chapter 1

Overview









1

Chapter 1 Overview











2







ISSN 0093-9994








March 2016




3

Chapter 1 Overview






4

Chapter 2

Introduction




COUT

S1

L2L1

D0

Input

Output

CIN


5

















6





S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN


S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN




φ = φ0 +VIN

N1tON (21)


7








φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)


VOUT =N2

N1

D1 minusD

VIN (26)



iL1 = iL1(0) +VIN

L1tON (27)


8



iL2 =N1

N2iL1 = N iL1 (28)


N =N1

N2=

radicL1

L2(29)


VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)


VDS(S1) = VIN +N1

N2VOUT (212)





9


213 Applications



COUT

S1

L2L1

UGRID

D0

CDC-link




10




COUT

S1

S2

L2L1

UGRID

CDC-link





11




Switching Frequency








Coupled Inductor


12


Snubber


S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT



Input EMI-Filter


13


22 Devices MOSFETs


221 Structure


G

D

S S

n+ n+

p p

n-

n+


G

D

S S

n+ n+

p p

n-

n+

p+p+



14

22 Devices MOSFETs





G

D

S

CGD

CGS

CDS



15



G

D

S S

n+ n+

p p

n-

n+

p+p+






16

22 Devices MOSFETs


223 Soft Switching



17

Chapter 3










19




S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER




20





S1

L2COUT

L1 VOUT

D0

CDC-link



S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link





21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time


S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time



22




VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)


L2

L2+Lσ2Lm


VOUT =N2





23







24




0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()





25

Chapter 4


41 Chapter Outline


27


42 Concept Overview


S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED


CONTROLLER




28










29



S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side


Slave Logic




30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold



QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic





31




gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST


32

Chapter 5


51 Chapter Outline










33


52 Voltage Sensing




minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2



34

52 Voltage Sensing





05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)



35








R2lt C1

dVDS(S1)

dt(51)




36

52 Voltage Sensing



R3minus

+

S2

QSR

D4

D5




COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2


37




gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold



38






N

Y

S2 ON


Y


Y

N


S2 OFF


N

Y

S2 ONS2 OFF

Pulse-skipping


Turn-ON Request


39




TON =

radic2L1PIN


(52)





40





2minus

Prated

CDC-link f grid(53)



Pneg =12





L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)


41










42





Connect to Grid


Send lowpower pulse

Wait


N

Y


Wait

Sample VOUT


N

Y


Send turn-ONrequest


N

Y

Enter Steady State


Y


43




541 Control Boards






44




1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)










45


543 Power Board


Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link







46


S1Driver

Diode Bridge


Sensing

S2Driver

Snubber Diode

AdditionalCOUT








47
















48



















49





106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)




50




0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2





51




Device Stresses



S1 S2 Occurs during






52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)





53





20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro





54







55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



56







FPGA 37 37



TOTAL 113 111



57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)






58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)



14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo


t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)



59




0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()






60


555 Loss Breakdown






61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore


Other


10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate



S2 condS2 gate


62


Leakage Inductance




σ 284microH


Core Material




63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other


64

56 Conclusion



56 Conclusion




65






66

Chapter 6


61 Chapter Outline







67






gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS


68




QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)



INEG =





69





C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6



R8

C5

minus+

minus

+

Qslope

UslopeS1


70



C5d VDS(S1)

dtgt

Uslope

R8(65)





R9

C6

minus

+

minus

+

S2

SSF

QSR

USF




71





tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts


72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired





73



gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait



TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)


74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R




S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link


Regulation




75





2minus

POUT

CDC-link f grid(67)


Pneg =12




L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)


76





Coupled Inductor

S2

Secondary Side

COUT


Input EMI-Filter








77






Power Board

AC InputConnections


Auxilliary Voltages






78














79














80














81



661 Primary Side


0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)





82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)



662 Secondary Side





83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



84

67 VOT Measurements

67 VOT Measurements












85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)



0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)



86

67 VOT Measurements


870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)



672 Load Jumps


87




0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)





88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)






89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)



220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k



90



681 Measurements






0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding







92



20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)







93


69 Conclusions








94

Chapter 7


71 Chapter Outline





95





0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)




96









722 Hardware


R10

R11

minus

+

minus

+

S2

QSOFT

USOFT


97






0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)



98






20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq




99


724 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()


Low-LineHigh-Line



100

73 VF-VOT Concept

73 VF-VOT Concept



Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER


101












102

73 VF-VOT Concept




0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)





103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept



20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S



105


734 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()





106

73 VF-VOT Concept



0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()


Falling FREF


107










108












109



gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT


tNEG(R)++

20 V VOUTthreshold


tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1


110





L1 VOUTTLOWER (71)


0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)





111



tNEG(R) gt1

VOUT



744 Measurements







112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V






113


75 Conclusion





114

Chapter 8

Conclusions

81 Summary








115


811 Feasibility




812 Viability


116

81 Summary




813 Capability



117













118








119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF




0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS


e-mode GaN 52 mΩ



120


Abbreviations









121


Symbols

Component Parameter
































id A Drain current

122














PIN W Input power

Ploss W Power loss






















123






































124

Bibliography











125

BIBLIOGRAPHY










126

BIBLIOGRAPHY











127

BIBLIOGRAPHY











128

BIBLIOGRAPHY










129

BIBLIOGRAPHY









130

BIBLIOGRAPHY













131

BIBLIOGRAPHY











132

BIBLIOGRAPHY









133

BIBLIOGRAPHY







134

Appendix A














135







136

Abstract


Acknowledgements

Overview

Thesis Objectives



Structure of Thesis

Introduction




Applications



Devices MOSFETs

Structure


Soft Switching





Flyback Efficiency


Chapter Outline

Concept Overview





Chapter Outline

Voltage Sensing









Control Boards


Power Board





Start-Up Routine


Loss Breakdown




Conclusion


Chapter Outline

Q-ZVS Improvement





Proposed Concept


Start-Up Routine



150 kHz Power Board



EMI-Filter for VOT



Primary Side

Secondary Side

VOT Measurements


Load Jumps



Measurements


Conclusions


Chapter Outline



Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept



Efficiency


Proposed Concept



Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability




Reverse Power Flow


Bibliography


Zusammenfassung


VII

Acknowledgements









Thank you all

IX

Chapter 1

Overview









1

Chapter 1 Overview











2







ISSN 0093-9994








March 2016




3

Chapter 1 Overview






4

Chapter 2

Introduction




COUT

S1

L2L1

D0

Input

Output

CIN


5

















6





S1

L2L1

D0

COUT+

+

iL1

VOUT

VIN

CIN


S1

L2L1

D0

COUT+

+

iL2

VOUT

VIN

CIN




φ = φ0 +VIN

N1tON (21)


7








φ(TS) = φ(0) +VIN

N1tON minus

VOUT


φ(TS) = φ(0) (25)


VOUT =N2

N1

D1 minusD

VIN (26)



iL1 = iL1(0) +VIN

L1tON (27)


8



iL2 =N1

N2iL1 = N iL1 (28)


N =N1

N2=

radicL1

L2(29)


VL2 = VOUT (210)

VL1 =N1

N2VL2 =

N1

N2VOUT (211)


VDS(S1) = VIN +N1

N2VOUT (212)





9


213 Applications



COUT

S1

L2L1

UGRID

D0

CDC-link




10




COUT

S1

S2

L2L1

UGRID

CDC-link





11




Switching Frequency








Coupled Inductor


12


Snubber


S1

S2

L2L1

UGRID

CDC-link

RSnCSn

DSn COUT



Input EMI-Filter


13


22 Devices MOSFETs


221 Structure


G

D

S S

n+ n+

p p

n-

n+


G

D

S S

n+ n+

p p

n-

n+

p+p+



14

22 Devices MOSFETs





G

D

S

CGD

CGS

CDS



15



G

D

S S

n+ n+

p p

n-

n+

p+p+






16

22 Devices MOSFETs


223 Soft Switching



17

Chapter 3










19




S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

CLASSIC

CONTROLLER




20





S1

L2COUT

L1 VOUT

D0

CDC-link



S1

L2

L3RA

RB

COUT

L1 VOUT

D0

CDC-link





21


S1

iL2

iL1

VRB

im

01

0 A

0 A

0 V

Time


S1

iL2

im

iL1

VRB

minusiL1

01

0 A

0 A

0 V

Time



22




VOUT =N2

N3

RA + RB

RBk VRB minus RB

N1

N2iL1 minus VD (31)


L2

L2+Lσ2Lm


VOUT =N2





23







24




0 20 40 60 80 10070

75

80

85

90

95

Load ()

Effici

ency

()





25

Chapter 4


41 Chapter Outline


27


42 Concept Overview


S1

S2

L2

COUT

L1

UGRID

VOUT

CDC-link

PROPOSED


CONTROLLER




28










29



S1

S2

L2

COUT

L1

UGRID

VOUT

VDS(S1)CDC-link

Secondary Side


Slave Logic




30


gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

TimeTNEG

INEG

ZVS

VOUTthreshold



QCOSS =

int VDS

0COSS(V) dV (41)

INEG =radic





31




gate(S2)

iL2

VDS(S2)

gate(S1)

iL1

VDS(S1)

VOUT

TimeREQUEST

VOUT

threshold

REQUEST


32

Chapter 5


51 Chapter Outline










33


52 Voltage Sensing




minus

+ U1

R2

C1

R1minus

+

QPRI

S1

C2D3

D1

D2



34

52 Voltage Sensing





05 15 2 25 3 35

0

2

4

6

8

10

12

14

16

0

50

100

150

200

250

300

350

400

Time (micros)

QPR

I(V

)ampV

GS

(V)

VD

S(S1

)(V

)



35








R2lt C1

dVDS(S1)

dt(51)




36

52 Voltage Sensing



R3minus

+

S2

QSR

D4

D5




COUT

R4

R5

minus

+ UREF

minus

+

S2

QOUT

L2


37




gate(S2)

iL2

gate(S1)

iL1

VOUT

VDC-link

Timetwait twait

VOUT

threshold



38






N

Y

S2 ON


Y


Y

N


S2 OFF


N

Y

S2 ONS2 OFF

Pulse-skipping


Turn-ON Request


39




TON =

radic2L1PIN


(52)





40





2minus

Prated

CDC-link f grid(53)



Pneg =12





L1 =1

2 f S(max)A2(radic

PIN +radic

Pneg)2(56)

whereA =

1VDC-link(min)

+1

NVOUT(57)


41










42





Connect to Grid


Send lowpower pulse

Wait


N

Y


Wait

Sample VOUT


N

Y


Send turn-ONrequest


N

Y

Enter Steady State


Y


43




541 Control Boards






44




1f S

= TNEG + 2PINL1

( 1VIN

2 +1

NVINVOUT+

1N2VOUT

2

)(58)










45


543 Power Board


Coupled Inductor

S2

Secondary Side

COUT

Primary Side

CDC-link







46


S1Driver

Diode Bridge


Sensing

S2Driver

Snubber Diode

AdditionalCOUT








47
















48



















49





106 108 110 112 114 116 118 120 122

0

10

20

0

200

400

t (micros)

i L2

(A)

VD

S(S1

)(V

)




50




0 2 4 6 8 10 12 14 16

0

10

20

1950

1975

2000

2025

2050

t (micros)

i L2

(A)

VO

UT

(V)

mdash VOUTmdash iL2





51




Device Stresses



S1 S2 Occurs during






52


0 5 10 15 20 25

300

200

100

0

4

3

2

1

0

0

25

50

75

t (micros)

VD

S(S1

)(V

)Q

SR(V

)ampG

ate

Sign

al(V

)

VD

S(S2

)(V

)





53





20 40 60 80 1000

50

100

150

200

250

300

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

085

130

175

Prim

ary

ON

-tim

e(micro





54







55


1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

100

200

300

400

500

600

Delay = 71 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



1 15 2 25 3 35 4 45

0

1

2

3

4

5

6

0

50

100

150

200

250

300

Delay = 75 ns

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)



56







FPGA 37 37



TOTAL 113 111



57


3 4 5 6 7 8 9 10 11

0

1

2

3

4

5

0

100

200

300

t (micros)

QPR

I(V

)amp

Gat

eSi

gnal

(V)

VD

S(S1

)(V

)






58


0 25 50 75 100 125 1500

100

200

300 0

10

20

ldquoHandshakerdquo

t (ms)

VD

S(S1

)(V

)

VO

UT

(V)



14184 14186 14188 141900

100

200

300

0

2

4

Full power pulse

Charging pulses

ldquoHandshakerdquo


t (ms)

VD

S(S1

)(V

)

Gat

eSE

C(V

)



59




0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()






60


555 Loss Breakdown






61


10 20 30 40 50 60 70 80 90 1000

2

4

6

8

10

12

Load ()

Loss

(W)

SnubberCore


Other


10 20 30 40 50 60 70 80 90 1000

02

04

06

08

1

12

Load ()

Loss

(W)

Input CapOutput Cap

S1 condS1 gate



S2 condS2 gate


62


Leakage Inductance




σ 284microH


Core Material




63


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

9

10

Load ()

Loss

(W)

SnubberCore


Other


64

56 Conclusion



56 Conclusion




65






66

Chapter 6


61 Chapter Outline







67






gate(S2)

iL2

gate(S1)

iL1

VDS(S1)

VOUT

Qslope

Qqzvs

Time

VOUT

threshold

TNEG

INEG

VQZVS


68




QCOSS(S1) =

int VDS

VQZVS

COSS(S1)(V) dV (61)



INEG =





69





C4

C3

R7

minus

+

Qqzvs

S1minus

+ Uq

R6



R8

C5

minus+

minus

+

Qslope

UslopeS1


70



C5d VDS(S1)

dtgt

Uslope

R8(65)





R9

C6

minus

+

minus

+

S2

SSF

QSR

USF




71





tON

f R

gate(S1)

iL1

VOUT

VDC-link

Time

VOUTthreshold

FREF FREF

ts ts+ ts+ ts


72


tON

f R

gate(S1)

iL1

gate(S2)

iL2

VOUT

OutputLoad

Time

VOUTthreshold

FREF FREF

Tdesired Tdesired





73



gate(S2)

iL2

gate(S1)

iL1

100 Load

VOUT

OutputLoad

Time

VOUTthreshold

twait twait twait



TUPPER =

radic2L1PIN

VDC-link(min)2 f S

(66)


74


Primary VOT Control

Kp

1Ti

intPlant

(Flyback)

1 FREF +

+

+

minus

1 f Rts

tON f R




S1

S2

L2COUT

L1

UGRID

VOUT

VDS(S1)CDC-link


Regulation




75





2minus

POUT

CDC-link f grid(67)


Pneg =12




L1 =1

2 f SA2(radic

PIN +radic

Pneg)2(610)

whereA =

1VDC-link(min)

+1

NVOUT(611)


76





Coupled Inductor

S2

Secondary Side

COUT


Input EMI-Filter








77






Power Board

AC InputConnections


Auxilliary Voltages






78














79














80














81



661 Primary Side


0 1 2 3 4 5 6 7-2

0

2

4

6

8

10

12

14

16

-60

0

60

120

180

240

300

360

420

580

t (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)





82


0 02 04 06 08 10 12

-2

0

2

4

6

8

10

-60

0

60

120

180

240

300

Time (micros)

i L2

(A)

ampQ

slop

e(V

)amp

Qqz

vs(V

)

VD

S(S1

)(V

)



662 Secondary Side





83


10 15 20 25 30

-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



10 15 20 25 30-2

0

2

4

6

8

1019820

202204

t (micros)

i L2

(A)

ampQ

SR(V

)

VO

UT

(V)



84

67 VOT Measurements

67 VOT Measurements












85


0 5 10 15 20 25 30 35

0

125

250

375

500

0

5

10

15

20

t (micros)

VD

S(S1

)(V

)

i L2

(A)



0 2 4 6 8 10 12 14 16

140150160

300310320330

-505101520

t (ms)

VD

C-l

ink

(V)

f s(k

Hz)

i L2

(A)



86

67 VOT Measurements


870 ns 870 ns

930 ns

105micros

5 10 15 20 25 30

0

5

10

195205

140

160

180

200

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)



672 Load Jumps


87




0 50 100 150

0

5

10

195205

140160180200220240

t (micros)

VO

UT

(V)

i L2

(A)

f s(k

Hz)





88

67 VOT Measurements

-20 0 20 40 60 80 100 120 1400

150

300

450

600

750

900

0

5

10

15

t (micros)

f s(k

Hz)

ampt O

N(n

s)

i L2

(A)






89


0 40 80 120 160 200 240 280 320012345

18192021

145150155160

170

180

190

200

t (micros)

VO

UT

(V)

i OU

T(A

)

f s(k

Hz)



220 230 240 250 260 270

-4-202468

10121416 140

150160170180190200

t (micros)

i L2

(A)

ampi O

UT

(A)

f s(k



90



681 Measurements






0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()




91


10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

8

Load ()

Loss

(W)

CoreWinding







92



20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

1

15

2

25

Prim

ary

ON

-tim

e(micro

s)







93


69 Conclusions








94

Chapter 7


71 Chapter Outline





95





0 2 4 6 8 10 12 14 16 18 20-5

0

5

10

15

0

20

40

60

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)




96









722 Hardware


R10

R11

minus

+

minus

+

S2

QSOFT

USOFT


97






0 2 4 6 8 10 12-4

0

4

8

12

16

-20

0

20

40

60

80

QOUTQSOFT

S2

t (micros)

i L1

(A)

ampi L

2(A

)

VD

S(S2

)(V

)



98






20 40 60 80 100

130

140

150

160

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

Max FreqMin Freq




99


724 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()


Low-LineHigh-Line



100

73 VF-VOT Concept

73 VF-VOT Concept



Decreasef REF

DecreasetON

IncreasetON

Increasef REF

Measuref R

enforcelimits

enforcelimits

Yes

NoYes

No

More power needed

Less power needed

f R gt f REF

f R lt f REF

VOT

VF(COT)

VF(COT)

VOT

tON = TUPPER

f R = FLOWER


101












102

73 VF-VOT Concept




0 2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)





103


2 4 6 8 10 12 14 16 18 20

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



2 4 6 8 10 12 14 16

90

110

130

150

170

08

14

2

26

32

t (ms)

f s(k

Hz)

ampV

DC

-lin

k(V

)

t ON

(micros)



104

73 VF-VOT Concept



20 40 60 80 100

90

110

130

150

Load ()

Swit

chin

gFr

eque

ncy

(kH

z)

05

15

25

35

Prim

ary

ON

-tim

e(micro

s)

Low-Line Max tON

Low-Line Min tON

High-Line Max tON

High-Line Min tON

Low-line Max f S

Low-line Min f S

High-line Max f S

High-line Min f S



105


734 Efficiency


0 20 40 60 80 10070

75

80

85

90

Load ()

Effici

ency

()





106

73 VF-VOT Concept



0 10 20 30 40 50 6075

80

85

90

Output Power (W)

Effici

ency

()


Falling FREF


107










108












109



gate(S2)

iL2

gate(S1)

iL1

VOUT

VDS(S1)

VDS(S2)

QSOFT


tNEG(R)++

20 V VOUTthreshold


tiL1REF

tiL1

tiL1tiL1

tiL1

tiL1


110





L1 VOUTTLOWER (71)


0 05 10 15 20 25 30

-3

-2

-1

0

1

2

3

4

5

0

60

120

180

240

300

S1

S2

t (micros)

i L1

(A)

ampi L

2(A

)amp

Gat

eSi

gnal

s

VD

S(S1

)(V

)





111



tNEG(R) gt1

VOUT



744 Measurements







112


0 10 20 30 40 50 60 70-5

0

5

10

15

20

25

t (ms)

i L2

(A)

ampV

OU

T(V






113


75 Conclusion





114

Chapter 8

Conclusions

81 Summary








115


811 Feasibility




812 Viability


116

81 Summary




813 Capability



117













118








119


x =ENEG(R)

EPOS(R)(81)

tDIS asymp1

FRPF




0 20 40 60 80

20

40

60

80

100

120

x ()

t DIS


e-mode GaN 52 mΩ



120


Abbreviations









121


Symbols

Component Parameter
































id A Drain current

122














PIN W Input power

Ploss W Power loss






















123






































124

Bibliography











125

BIBLIOGRAPHY










126

BIBLIOGRAPHY











127

BIBLIOGRAPHY











128

BIBLIOGRAPHY










129

BIBLIOGRAPHY









130

BIBLIOGRAPHY













131

BIBLIOGRAPHY











132

BIBLIOGRAPHY









133

BIBLIOGRAPHY







134

Appendix A














135







136

Abstract


Acknowledgements

Overview

Thesis Objectives



Structure of Thesis

Introduction




Applications



Devices MOSFETs

Structure


Soft Switching





Flyback Efficiency


Chapter Outline

Concept Overview





Chapter Outline

Voltage Sensing









Control Boards


Power Board





Start-Up Routine


Loss Breakdown




Conclusion


Chapter Outline

Q-ZVS Improvement





Proposed Concept


Start-Up Routine



150 kHz Power Board



EMI-Filter for VOT



Primary Side

Secondary Side

VOT Measurements


Load Jumps



Measurements


Conclusions


Chapter Outline



Hardware

Frequency Variation

Efficiency

VF-VOT Concept

Proposed Concept



Efficiency


Proposed Concept



Measurements

Conclusion

Conclusions

Summary

Feasibility

Viability

Capability




Reverse Power Flow


Bibliography


secondary side controlled flyback converter

Documents