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8/13/2019 Luis Terrazas

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AbstractAn analytical extrinsic gatecapacitance model based on three-

dimensional numerical simulations for

Triple Gate FinFET, was developed.

The model considers the source/drain

electrode and contact areas. It iscompound for 9 capacitance

components which describes the

different fringing electrical couplings

that appears inside the FinFET

structure. The analytical model

accurately calculates the total extrinsic

gate capacitance as function of main

geometrical parameters of Triple-Gate

FinFET.

Index TermsFinFETs, ExtrinsicCapacitance, Fringing Gate

Capacitance, Fringing Electric Field.

I. INTRODUCTION

The last years, FinFET has demonstrated

be a promising candidate to carry on with

downscaling of CMOS technology, due to

his superior control of the short channeleffects (SCE). Nevertheless, since their

three-dimensional structure, FinFETs

show high parasitic resistances andcapacitances which lead to strong

degradation of their analog and RF

performance [1][2]. Improvements can bereached, especially concerning to

reduction of the total extrinsic gate

capacitance (Cgge).

The FinFETs RF model is based on the

well-known small-signal equivalent

circuit (SS-EC) and implies an accurate

determination both intrinsic and extrinsicparameters. Thus, a compact model which

determine the DC and intrinsic RFparameters was demonstrated [3]. To

complete the SS-EC, is requiered an

accurate extrinsic capacitance modelwhich are strongly dependent on the

FinFET geometry. Recently, Wu and

Chan [1] developed a semi-analytical

model to describe total extrinsic gate

capacitance of double-gate FinFETs. Fig.

1a shows a schematic representation ofthe structure used and identifies the main

FinFET geometrical parameters. Threecapacitance components associated to theFinFET structure were considered, as

Figs. 1b to 1d

Figure 1 FiFET hi i i h 2 schematic representations of the different

capacitance components associated to the 3-D

structure.

the gate electrode to the internal side of

h S/D fi xi I h the S/D electrode regions are not

considered and thus some important

parasitic capacitances are not modeledwhile they are not negligible.

In this paper, based on 3-D numerical

simulations, a semi-analytical model for

the extrinsic gate capacitances for Triple-

Gate FinFETs is presented. This modelincludes the S/D electrode and contact

areas and the interactions between gatesin order to overcome the limitations ofprevious models and thus provide a

complete and accurate modeling of the

total extrinsic gatecapacitance valid for

a wide range of FinFET geometries.


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II. THE COMPACT MODEL

In a tridimensional FinFET structure

there are some typical capacitor

structures like: (I) parallel plate

capacitor, (II) perpendicular platecapacitor, (III) flat plate non parallel

capacitor, (IV) fringing field

capacitive component, (V)

Capacitancia de una lnea bifilar

monofsica

Structure Expresion

(I)

(II) (III) (IV) (V)

Table 1. Simple capacitance expressions

Including the S/D contact reas and

the capacitance effects between gates,

based on the classical capacitance

formulations presented in Table I, we

propose a compac model with nineextrinsic capacitance components as

illustrated Figure 2.

Figure 2. Schematic representations of the fivecapacitance components, C1-C9, considered in our

proposed compact model.

The firstcomponent C1 (Fig. 2a) can

be represented as flat-plate non-

parallel structure, exhibing

dependence with Lfin, Lext, Wfin, Tpoly,

and tox, and can be expressed as:

a) b)

c)d)

e) f)

g) h)

i)

(1)


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we divide these components in two cases,

for inner case (between gates) was

developed C1i and for the outer case C1e(for FinFET end)

C2 component (Fig 2b), depends of Lext,Wfin, Tpoly, and tox, similarly to C1 have

two cases and its base on perpendicular

plate capacitor case.

C3 component was developed taking on

account that both capacitances parallelplate and perpendicular plate occurs at the

same time, showing dependance of Hfin,

Sfin, Lextand tox

C4come in to a flat plate non parallel

capacitance, which corresponds to the

capacitance from the top of the gate

electrode to the top the S/D contact

regin and exhibits dependences with

of Tpoly, Lext, Sfinand Wcon

C5 was obtained with perpendicularplate capacitor case, thos component

correspond from the side of the gate

electrode located above the fin spacing

and the top of the S/D contact regin

Four cases were developed consideringthat there are capacitive effect between

the gates. The first one Considering aparallel plate capacitor we derive C6

component, which depends of separation

between gates (2(Lext)+Wcon) with lenghtSfin+Wfin and high Tpoly+tox.

( ) For C7 component was based (V) case,by not considering cilinders, neglecting and taking r as gate width

C8 and C9 component was developed

observing that wasnt previously

considered the effect of the gate side

(Tpoly) to the internal contact portion

and the lower adjacent gate

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)


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Because RF transistors consist of

multi-fin devices, the total gate

capacitance per gate finger is definedby the sum of the whole components

expressed by (1)-(9), considering that

we develop the model with inner and

outer components we add the

components as:

( )

[ ]

III. SIMULATIONS

Tridimensional finite element numerical

simulations were performed in order toverify the developed compact. Simple

structures were used to analyze each

capacitance component, finally the fullFinFET structure was used to verify the

total gate capacitance.

IV. RESULTS

V. CONCLUSION

An analytical model for extrinsic gatecapacitance for Triple-Gate FinFET is

presented. The model considers he S/D

contact region and includes fivecapacitance components. It is based on

simple capacitor structures and describes

the dependences with the maingeometrical FinFET parameters: Lext,

Wcon, Sfin, Wfin, Lfin and Hfin. The

compact model has been validated for a

wide range of FinFETs dimensions.

Simulation results show optimizationpaths to decrease the impact of extrinsic

capacitances, such as the reduction of finspacing Sfin, the S/D fin extensionLext aswell as by increasing the fin aspect ratio

(Hfin/Wfin). The proposed compact

model is of great interest for designers

considering FinFET technology for high-speed digital and RF applications.

REFERENCES

1 M Ch Ayi fgeometry-dependent parasitics in multifin

Double-G FiFET IEEE TED v54, no. 4, pp. 692-698, April 2007.

2 J C Ti I fextrinsic capacitances on FinFETs RFf i 2012 12h SiRF 73-76.

3 J Av C S-Sig M f RF FiFET i 20128th ICCDCS.

4 D G O-chip interconnect-aware design and modeling methodology,based on high bandwidth transmissioni vi i 2003 41 DAC 724-727.


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