ivnc 2013 presentation guerrera

8/12/2019 IVNC 2013 Presentation Guerrera

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Self-Aligned, Gated Field Emitter

Arrays with Integrated High-

Aspect-Ratio Current LimitersStephen A. Guerrera

Akintunde I. Akinwande

Microsystems Technology LaboratoriesDepartment of Electrical Engineering and Computer Science

Massachusetts Institute of TechnologyCambridge, MA 02139

[email protected]

IVNC 2013 07/11/2013


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Overview Introduction and Motivation Device Design and Analysis Device Fabrication

Device Characterization

ConclusionsIVNC 2013 7/11/20132


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Overview Introduction and Motivation Device Design and Analysis Device Fabrication

Device Characterization

ConclusionsIVNC 2013 7/11/20133


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Applications of Cold Field Emitters

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!"#$ &'(&)* +,-./01)2.3

41&& 5#&6-1/7 +)8&18 9&1).&1-: ;/"16&8

*)0,70

>/7,:&18 ?/1


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Silicon Field EmissionTwo-Step Problem

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2D Fermi sea of electrons

J=qnv F

Ef e-E

c

Flux of electrons

to the surface

Transmission ofelectrons through

the barrier

Transmission Limited Regime: - Electron emission is strongly dependent on the emitter tip radius and

work function

Supply Limited Regime: - Electron emission is largely independent of tip radius and work

function


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Tip Radius Statistical Distribution

Results in Array Underutilization

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r0r0-3! r0+3!

Burn-out limit: 10-6A

1LV ML 7*

!V K 7*


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Vertical Current Limiters Can

Increase Uniformity and Reliability

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Overview Introduction and Motivation Device Design and Analysis Device Fabrication Device Characterization Conclusions

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Previous Results

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5 um pitch 10 um tall, 100 nm

diameter current

limiters

Tip radius < 10nm Perforated, metallizedextraction grid ~12 um

from tips


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Previous Results

bFN= 2942 Turn-on voltage ~ 130 V

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How Do We Get Low Turn-on

Voltage?

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Turn-On Voltage of Si Field

Emitters

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Iondefined as 100 pA arraycurrent for our samples

Many, many di"erentchoices in the literature

Experimental Slope: 0.0377 Theory:

Assume turn-on field of 2x107V/cm

dVON/ dbFN= 0.0376 Experimental y-intercept:

4.156 (~#si?)

R2: 0.951


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Overview Introduction and Motivation Design and Analysis Device Fabrication Device Characterization Conclusions

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Fabrication Process

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Fabrication Process Contd

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Completed Device Structure

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Gate aperture diameter: ~300 nm Poly-Si thickness: ~200 nm Tip radius:


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Completed Device Structure

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Gate aperture diameter: ~350 nm Poly-Si thickness: ~200 nm Tip radius:


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Overview Introduction and Motivation Design and Analysis Device Fabrication Device Characterization Conclusions

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Testing Parameters

Pressure: 5x10-9Torr # of emitters: 1x106

Pitch: 1 micron

Array area : 1 mm2 Anode: Silicon plate Emitter-anode separation: 1 cm

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;,


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Preliminary I-V Characterization

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Turn-on < 20 V


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Preliminary I-V Characterization

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bFN

= 277

LN(aFN

) = -16


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Overview Introduction and Motivation Design and Analysis Fabrication Characterization Conclusions

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Conclusions Developed a fabrication process for filling in the

gaps between dense high-aspect-ratio pillars

Fabricated 1um pitch field emitters arrays withintegrated high-aspect-ratio current limiters andself-aligned gates

Demonstrated low turn on voltage devices (


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Conclusions

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Future Work Improve array uniformity

Improve design for testability (ie. includecontact pads)

Explore surface treatments and coatings

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Acknowledgements These devices were fabricated using the Microsystems

Technology Laboratories

Thanks to the lab sta"for assistance

Dr. L. F. Velasquez-Garcia for useful discussions andinitial proof of concept of the vertical current limiters

This work was supported in part by DARPA awardnumber N66001-12-1-4212, program manager Dr.

Joseph Mangano

IVNC 2013 7/11/201326


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